1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
|
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/*
*
* Interface to the SMI/MDIO hardware, including support for both IEEE 802.3
* clause 22 and clause 45 operations.
*
*/
#ifndef __CVMX_MIO_H__
#define __CVMX_MIO_H__
#include "cvmx-smix-defs.h"
/**
* PHY register 0 from the 802.3 spec
*/
#define CVMX_MDIO_PHY_REG_CONTROL 0
typedef union {
uint16_t u16;
struct {
uint16_t reset:1;
uint16_t loopback:1;
uint16_t speed_lsb:1;
uint16_t autoneg_enable:1;
uint16_t power_down:1;
uint16_t isolate:1;
uint16_t restart_autoneg:1;
uint16_t duplex:1;
uint16_t collision_test:1;
uint16_t speed_msb:1;
uint16_t unidirectional_enable:1;
uint16_t reserved_0_4:5;
} s;
} cvmx_mdio_phy_reg_control_t;
/**
* PHY register 1 from the 802.3 spec
*/
#define CVMX_MDIO_PHY_REG_STATUS 1
typedef union {
uint16_t u16;
struct {
uint16_t capable_100base_t4:1;
uint16_t capable_100base_x_full:1;
uint16_t capable_100base_x_half:1;
uint16_t capable_10_full:1;
uint16_t capable_10_half:1;
uint16_t capable_100base_t2_full:1;
uint16_t capable_100base_t2_half:1;
uint16_t capable_extended_status:1;
uint16_t capable_unidirectional:1;
uint16_t capable_mf_preamble_suppression:1;
uint16_t autoneg_complete:1;
uint16_t remote_fault:1;
uint16_t capable_autoneg:1;
uint16_t link_status:1;
uint16_t jabber_detect:1;
uint16_t capable_extended_registers:1;
} s;
} cvmx_mdio_phy_reg_status_t;
/**
* PHY register 2 from the 802.3 spec
*/
#define CVMX_MDIO_PHY_REG_ID1 2
typedef union {
uint16_t u16;
struct {
uint16_t oui_bits_3_18;
} s;
} cvmx_mdio_phy_reg_id1_t;
/**
* PHY register 3 from the 802.3 spec
*/
#define CVMX_MDIO_PHY_REG_ID2 3
typedef union {
uint16_t u16;
struct {
uint16_t oui_bits_19_24:6;
uint16_t model:6;
uint16_t revision:4;
} s;
} cvmx_mdio_phy_reg_id2_t;
/**
* PHY register 4 from the 802.3 spec
*/
#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4
typedef union {
uint16_t u16;
struct {
uint16_t next_page:1;
uint16_t reserved_14:1;
uint16_t remote_fault:1;
uint16_t reserved_12:1;
uint16_t asymmetric_pause:1;
uint16_t pause:1;
uint16_t advert_100base_t4:1;
uint16_t advert_100base_tx_full:1;
uint16_t advert_100base_tx_half:1;
uint16_t advert_10base_tx_full:1;
uint16_t advert_10base_tx_half:1;
uint16_t selector:5;
} s;
} cvmx_mdio_phy_reg_autoneg_adver_t;
/**
* PHY register 5 from the 802.3 spec
*/
#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5
typedef union {
uint16_t u16;
struct {
uint16_t next_page:1;
uint16_t ack:1;
uint16_t remote_fault:1;
uint16_t reserved_12:1;
uint16_t asymmetric_pause:1;
uint16_t pause:1;
uint16_t advert_100base_t4:1;
uint16_t advert_100base_tx_full:1;
uint16_t advert_100base_tx_half:1;
uint16_t advert_10base_tx_full:1;
uint16_t advert_10base_tx_half:1;
uint16_t selector:5;
} s;
} cvmx_mdio_phy_reg_link_partner_ability_t;
/**
* PHY register 6 from the 802.3 spec
*/
#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6
typedef union {
uint16_t u16;
struct {
uint16_t reserved_5_15:11;
uint16_t parallel_detection_fault:1;
uint16_t link_partner_next_page_capable:1;
uint16_t local_next_page_capable:1;
uint16_t page_received:1;
uint16_t link_partner_autoneg_capable:1;
} s;
} cvmx_mdio_phy_reg_autoneg_expansion_t;
/**
* PHY register 9 from the 802.3 spec
*/
#define CVMX_MDIO_PHY_REG_CONTROL_1000 9
typedef union {
uint16_t u16;
struct {
uint16_t test_mode:3;
uint16_t manual_master_slave:1;
uint16_t master:1;
uint16_t port_type:1;
uint16_t advert_1000base_t_full:1;
uint16_t advert_1000base_t_half:1;
uint16_t reserved_0_7:8;
} s;
} cvmx_mdio_phy_reg_control_1000_t;
/**
* PHY register 10 from the 802.3 spec
*/
#define CVMX_MDIO_PHY_REG_STATUS_1000 10
typedef union {
uint16_t u16;
struct {
uint16_t master_slave_fault:1;
uint16_t is_master:1;
uint16_t local_receiver_ok:1;
uint16_t remote_receiver_ok:1;
uint16_t remote_capable_1000base_t_full:1;
uint16_t remote_capable_1000base_t_half:1;
uint16_t reserved_8_9:2;
uint16_t idle_error_count:8;
} s;
} cvmx_mdio_phy_reg_status_1000_t;
/**
* PHY register 15 from the 802.3 spec
*/
#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15
typedef union {
uint16_t u16;
struct {
uint16_t capable_1000base_x_full:1;
uint16_t capable_1000base_x_half:1;
uint16_t capable_1000base_t_full:1;
uint16_t capable_1000base_t_half:1;
uint16_t reserved_0_11:12;
} s;
} cvmx_mdio_phy_reg_extended_status_t;
/**
* PHY register 13 from the 802.3 spec
*/
#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13
typedef union {
uint16_t u16;
struct {
uint16_t function:2;
uint16_t reserved_5_13:9;
uint16_t devad:5;
} s;
} cvmx_mdio_phy_reg_mmd_control_t;
/**
* PHY register 14 from the 802.3 spec
*/
#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14
typedef union {
uint16_t u16;
struct {
uint16_t address_data:16;
} s;
} cvmx_mdio_phy_reg_mmd_address_data_t;
/* Operating request encodings. */
#define MDIO_CLAUSE_22_WRITE 0
#define MDIO_CLAUSE_22_READ 1
#define MDIO_CLAUSE_45_ADDRESS 0
#define MDIO_CLAUSE_45_WRITE 1
#define MDIO_CLAUSE_45_READ_INC 2
#define MDIO_CLAUSE_45_READ 3
/* MMD identifiers, mostly for accessing devices withing XENPAK modules. */
#define CVMX_MMD_DEVICE_PMA_PMD 1
#define CVMX_MMD_DEVICE_WIS 2
#define CVMX_MMD_DEVICE_PCS 3
#define CVMX_MMD_DEVICE_PHY_XS 4
#define CVMX_MMD_DEVICE_DTS_XS 5
#define CVMX_MMD_DEVICE_TC 6
#define CVMX_MMD_DEVICE_CL22_EXT 29
#define CVMX_MMD_DEVICE_VENDOR_1 30
#define CVMX_MMD_DEVICE_VENDOR_2 31
/* Helper function to put MDIO interface into clause 45 mode */
static inline void __cvmx_mdio_set_clause45_mode(int bus_id)
{
union cvmx_smix_clk smi_clk;
/* Put bus into clause 45 mode */
smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
smi_clk.s.mode = 1;
smi_clk.s.preamble = 1;
cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
}
/* Helper function to put MDIO interface into clause 22 mode */
static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
{
union cvmx_smix_clk smi_clk;
/* Put bus into clause 22 mode */
smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
smi_clk.s.mode = 0;
cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
}
/**
* Perform an MII read. This function is used to read PHY
* registers controlling auto negotiation.
*
* @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
* support multiple busses.
* @phy_id: The MII phy id
* @location: Register location to read
*
* Returns Result from the read or -1 on failure
*/
static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
{
union cvmx_smix_cmd smi_cmd;
union cvmx_smix_rd_dat smi_rd;
int timeout = 1000;
if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
__cvmx_mdio_set_clause22_mode(bus_id);
smi_cmd.u64 = 0;
smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ;
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = location;
cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
do {
cvmx_wait(1000);
smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
} while (smi_rd.s.pending && timeout--);
if (smi_rd.s.val)
return smi_rd.s.dat;
else
return -1;
}
/**
* Perform an MII write. This function is used to write PHY
* registers controlling auto negotiation.
*
* @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
* support multiple busses.
* @phy_id: The MII phy id
* @location: Register location to write
* @val: Value to write
*
* Returns -1 on error
* 0 on success
*/
static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
{
union cvmx_smix_cmd smi_cmd;
union cvmx_smix_wr_dat smi_wr;
int timeout = 1000;
if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
__cvmx_mdio_set_clause22_mode(bus_id);
smi_wr.u64 = 0;
smi_wr.s.dat = val;
cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
smi_cmd.u64 = 0;
smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE;
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = location;
cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
do {
cvmx_wait(1000);
smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
} while (smi_wr.s.pending && --timeout);
if (timeout <= 0)
return -1;
return 0;
}
/**
* Perform an IEEE 802.3 clause 45 MII read. This function is used to
* read PHY registers controlling auto negotiation.
*
* @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
* support multiple busses.
* @phy_id: The MII phy id
* @device: MDIO Managable Device (MMD) id
* @location: Register location to read
*
* Returns Result from the read or -1 on failure
*/
static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device,
int location)
{
union cvmx_smix_cmd smi_cmd;
union cvmx_smix_rd_dat smi_rd;
union cvmx_smix_wr_dat smi_wr;
int timeout = 1000;
if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
return -1;
__cvmx_mdio_set_clause45_mode(bus_id);
smi_wr.u64 = 0;
smi_wr.s.dat = location;
cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
smi_cmd.u64 = 0;
smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = device;
cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
do {
cvmx_wait(1000);
smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
} while (smi_wr.s.pending && --timeout);
if (timeout <= 0) {
cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
"device %2d register %2d TIME OUT(address)\n",
bus_id, phy_id, device, location);
return -1;
}
smi_cmd.u64 = 0;
smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ;
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = device;
cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
do {
cvmx_wait(1000);
smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
} while (smi_rd.s.pending && --timeout);
if (timeout <= 0) {
cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
"device %2d register %2d TIME OUT(data)\n",
bus_id, phy_id, device, location);
return -1;
}
if (smi_rd.s.val)
return smi_rd.s.dat;
else {
cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
"device %2d register %2d INVALID READ\n",
bus_id, phy_id, device, location);
return -1;
}
}
/**
* Perform an IEEE 802.3 clause 45 MII write. This function is used to
* write PHY registers controlling auto negotiation.
*
* @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
* support multiple busses.
* @phy_id: The MII phy id
* @device: MDIO Managable Device (MMD) id
* @location: Register location to write
* @val: Value to write
*
* Returns -1 on error
* 0 on success
*/
static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device,
int location, int val)
{
union cvmx_smix_cmd smi_cmd;
union cvmx_smix_wr_dat smi_wr;
int timeout = 1000;
if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
return -1;
__cvmx_mdio_set_clause45_mode(bus_id);
smi_wr.u64 = 0;
smi_wr.s.dat = location;
cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
smi_cmd.u64 = 0;
smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = device;
cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
do {
cvmx_wait(1000);
smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
} while (smi_wr.s.pending && --timeout);
if (timeout <= 0)
return -1;
smi_wr.u64 = 0;
smi_wr.s.dat = val;
cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
smi_cmd.u64 = 0;
smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE;
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = device;
cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
do {
cvmx_wait(1000);
smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
} while (smi_wr.s.pending && --timeout);
if (timeout <= 0)
return -1;
return 0;
}
#endif
|
