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-rw-r--r--shared-core/drm.h4
-rw-r--r--shared-core/drm_sarea.h2
-rw-r--r--shared-core/i915_dma.c34
-rw-r--r--shared-core/i915_drm.h16
-rw-r--r--shared-core/i915_drv.h204
-rw-r--r--shared-core/i915_irq.c28
-rw-r--r--shared-core/i915_mem.c2
-rw-r--r--shared-core/mach64_dma.c8
-rw-r--r--shared-core/mach64_drv.h48
-rw-r--r--shared-core/mga_dma.c22
-rw-r--r--shared-core/mga_drm.h16
-rw-r--r--shared-core/mga_drv.h116
-rw-r--r--shared-core/mga_irq.c2
-rw-r--r--shared-core/mga_state.c10
-rw-r--r--shared-core/nouveau_dma.c1
-rw-r--r--shared-core/nouveau_dma.h1
-rw-r--r--shared-core/nouveau_drm.h1
-rw-r--r--shared-core/nouveau_drv.h3
-rw-r--r--shared-core/nouveau_fifo.c12
-rw-r--r--shared-core/nouveau_irq.c5
-rw-r--r--shared-core/nouveau_mem.c22
-rw-r--r--shared-core/nouveau_notifier.c3
-rw-r--r--shared-core/nouveau_object.c33
-rw-r--r--shared-core/nouveau_reg.h1
-rw-r--r--shared-core/nouveau_state.c10
-rw-r--r--shared-core/nouveau_swmthd.c2
-rw-r--r--shared-core/nouveau_swmthd.h1
-rw-r--r--shared-core/nv04_fb.c1
-rw-r--r--shared-core/nv04_fifo.c9
-rw-r--r--shared-core/nv04_graph.c2
-rw-r--r--shared-core/nv04_instmem.c3
-rw-r--r--shared-core/nv04_mc.c1
-rw-r--r--shared-core/nv04_timer.c1
-rw-r--r--shared-core/nv10_fb.c1
-rw-r--r--shared-core/nv10_fifo.c1
-rw-r--r--shared-core/nv10_graph.c5
-rw-r--r--shared-core/nv20_graph.c1
-rw-r--r--shared-core/nv40_fb.c1
-rw-r--r--shared-core/nv40_fifo.c1
-rw-r--r--shared-core/nv40_graph.c65
-rw-r--r--shared-core/nv40_mc.c1
-rw-r--r--shared-core/nv50_fifo.c1
-rw-r--r--shared-core/nv50_graph.c5
-rw-r--r--shared-core/nv50_instmem.c7
-rw-r--r--shared-core/r128_cce.c2
-rw-r--r--shared-core/r128_drv.h2
-rw-r--r--shared-core/r300_cmdbuf.c34
-rw-r--r--shared-core/r300_reg.h32
-rw-r--r--shared-core/radeon_cp.c10
-rw-r--r--shared-core/radeon_drm.h12
-rw-r--r--shared-core/radeon_drv.h56
-rw-r--r--shared-core/radeon_state.c2
-rw-r--r--shared-core/savage_bci.c9
-rw-r--r--shared-core/savage_drv.h4
-rw-r--r--shared-core/savage_state.c4
-rw-r--r--shared-core/via_dma.c44
-rw-r--r--shared-core/via_drm.h16
-rw-r--r--shared-core/via_drv.h8
-rw-r--r--shared-core/via_irq.c42
-rw-r--r--shared-core/via_map.c1
-rw-r--r--shared-core/via_verifier.c16
-rw-r--r--shared-core/via_verifier.h10
-rw-r--r--shared-core/xgi_drm.h6
63 files changed, 495 insertions, 528 deletions
diff --git a/shared-core/drm.h b/shared-core/drm.h
index 4059a6fb..39414902 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -703,7 +703,7 @@ struct drm_fence_arg {
/* Mask: Make sure the buffer is in cached memory when mapped
* Flags: Acknowledge.
* Buffers allocated with this flag should not be used for suballocators
- * This type may have issues on CPUs with over-aggressive caching
+ * This type may have issues on CPUs with over-aggressive caching
* http://marc.info/?l=linux-kernel&m=102376926732464&w=2
*/
#define DRM_BO_FLAG_CACHED_MAPPED (1ULL << 19)
@@ -925,7 +925,7 @@ struct drm_mm_init_arg {
#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
-#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
+#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
diff --git a/shared-core/drm_sarea.h b/shared-core/drm_sarea.h
index 34050a6d..8b677522 100644
--- a/shared-core/drm_sarea.h
+++ b/shared-core/drm_sarea.h
@@ -45,7 +45,7 @@
#endif
/** Maximum number of drawables in the SAREA */
-#define SAREA_MAX_DRAWABLES 256
+#define SAREA_MAX_DRAWABLES 256
#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000
diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index 18c3f0f0..4d77dfcf 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -3,7 +3,7 @@
/*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
@@ -11,11 +11,11 @@
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
@@ -23,7 +23,7 @@
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
+ *
*/
#include "drmP.h"
@@ -172,11 +172,11 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
/* Enable vblank on pipe A for older X servers
*/
- dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
+ dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
/* Program Hardware Status Page */
if (!IS_G33(dev)) {
- dev_priv->status_page_dmah =
+ dev_priv->status_page_dmah =
drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
if (!dev_priv->status_page_dmah) {
@@ -329,7 +329,7 @@ static int validate_cmd(int cmd)
{
int ret = do_validate_cmd(cmd);
-/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
+/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
return ret;
}
@@ -365,12 +365,12 @@ static int i915_emit_cmds(struct drm_device * dev, int __user * buffer,
OUT_RING(cmd);
}
}
-
+
if (dwords & 1)
OUT_RING(0);
ADVANCE_LP_RING();
-
+
return 0;
}
@@ -861,7 +861,7 @@ static int i915_exec_reloc(struct drm_file *file_priv, drm_handle_t buf_handle,
int ret = 0;
memset(&relocatee, 0, sizeof(relocatee));
-
+
mutex_lock(&dev->struct_mutex);
relocatee.buf = drm_lookup_buffer_object(file_priv, buf_handle, 1);
mutex_unlock(&dev->struct_mutex);
@@ -870,7 +870,7 @@ static int i915_exec_reloc(struct drm_file *file_priv, drm_handle_t buf_handle,
ret = -EINVAL;
goto out_err;
}
-
+
while (buf_reloc_handle) {
ret = i915_process_relocs(file_priv, buf_handle, &buf_reloc_handle, &relocatee, buffers, buf_count);
if (ret) {
@@ -878,11 +878,11 @@ static int i915_exec_reloc(struct drm_file *file_priv, drm_handle_t buf_handle,
break;
}
}
-
+
mutex_lock(&dev->struct_mutex);
drm_bo_usage_deref_locked(&relocatee.buf);
mutex_unlock(&dev->struct_mutex);
-
+
out_err:
return ret;
}
@@ -1012,12 +1012,12 @@ static int i915_execbuffer(struct drm_device *dev, void *data,
ret = drm_bo_read_lock(&dev->bm.bm_lock);
- if (ret)
+ if (ret)
return ret;
/*
* The cmdbuf_mutex makes sure the validate-submit-fence
- * operation is atomic.
+ * operation is atomic.
*/
ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);
@@ -1200,7 +1200,7 @@ drm_i915_mmio_entry_t mmio_table[] = {
I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
0x2350,
8
- }
+ }
};
static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
@@ -1210,7 +1210,7 @@ static int i915_mmio(struct drm_device *dev, void *data,
{
uint32_t buf[8];
drm_i915_private_t *dev_priv = dev->dev_private;
- drm_i915_mmio_entry_t *e;
+ drm_i915_mmio_entry_t *e;
drm_i915_mmio_t *mmio = data;
void __iomem *base;
int i;
diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index a6c3cf30..56977ff3 100644
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -1,7 +1,7 @@
/*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
@@ -9,11 +9,11 @@
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
@@ -21,7 +21,7 @@
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
+ *
*/
#ifndef _I915_DRM_H_
@@ -294,11 +294,11 @@ typedef struct drm_i915_vblank_swap {
unsigned int sequence;
} drm_i915_vblank_swap_t;
-#define I915_MMIO_READ 0
+#define I915_MMIO_READ 0
#define I915_MMIO_WRITE 1
-#define I915_MMIO_MAY_READ 0x1
-#define I915_MMIO_MAY_WRITE 0x2
+#define I915_MMIO_MAY_READ 0x1
+#define I915_MMIO_MAY_WRITE 0x2
#define MMIO_REGS_IA_PRIMATIVES_COUNT 0
#define MMIO_REGS_IA_VERTICES_COUNT 1
@@ -319,7 +319,7 @@ typedef struct drm_i915_mmio_entry {
typedef struct drm_i915_mmio {
unsigned int read_write:1;
unsigned int reg:31;
- void __user *data;
+ void __user *data;
} drm_i915_mmio_t;
typedef struct drm_i915_hws_addr {
diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
index 6ff34eb7..9ee79fac 100644
--- a/shared-core/i915_drv.h
+++ b/shared-core/i915_drv.h
@@ -1,10 +1,10 @@
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
*/
/*
- *
+ *
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
@@ -12,11 +12,11 @@
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
@@ -24,7 +24,7 @@
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
+ *
*/
#ifndef _I915_DRV_H_
@@ -146,76 +146,76 @@ typedef struct drm_i915_private {
drm_i915_vbl_swap_t vbl_swaps;
unsigned int swaps_pending;
- /* Register state */
+ /* Register state */
u8 saveLBB;
- u32 saveDSPACNTR;
- u32 saveDSPBCNTR;
- u32 savePIPEACONF;
- u32 savePIPEBCONF;
- u32 savePIPEASRC;
- u32 savePIPEBSRC;
- u32 saveFPA0;
- u32 saveFPA1;
- u32 saveDPLL_A;
- u32 saveDPLL_A_MD;
- u32 saveHTOTAL_A;
- u32 saveHBLANK_A;
- u32 saveHSYNC_A;
- u32 saveVTOTAL_A;
- u32 saveVBLANK_A;
- u32 saveVSYNC_A;
+ u32 saveDSPACNTR;
+ u32 saveDSPBCNTR;
+ u32 savePIPEACONF;
+ u32 savePIPEBCONF;
+ u32 savePIPEASRC;
+ u32 savePIPEBSRC;
+ u32 saveFPA0;
+ u32 saveFPA1;
+ u32 saveDPLL_A;
+ u32 saveDPLL_A_MD;
+ u32 saveHTOTAL_A;
+ u32 saveHBLANK_A;
+ u32 saveHSYNC_A;
+ u32 saveVTOTAL_A;
+ u32 saveVBLANK_A;
+ u32 saveVSYNC_A;
u32 saveBCLRPAT_A;
- u32 saveDSPASTRIDE;
- u32 saveDSPASIZE;
- u32 saveDSPAPOS;
- u32 saveDSPABASE;
- u32 saveDSPASURF;
+ u32 saveDSPASTRIDE;
+ u32 saveDSPASIZE;
+ u32 saveDSPAPOS;
+ u32 saveDSPABASE;
+ u32 saveDSPASURF;
u32 saveDSPATILEOFF;
u32 savePFIT_PGM_RATIOS;
u32 saveBLC_PWM_CTL;
u32 saveBLC_PWM_CTL2;
- u32 saveFPB0;
- u32 saveFPB1;
- u32 saveDPLL_B;
- u32 saveDPLL_B_MD;
- u32 saveHTOTAL_B;
- u32 saveHBLANK_B;
- u32 saveHSYNC_B;
- u32 saveVTOTAL_B;
- u32 saveVBLANK_B;
- u32 saveVSYNC_B;
+ u32 saveFPB0;
+ u32 saveFPB1;
+ u32 saveDPLL_B;
+ u32 saveDPLL_B_MD;
+ u32 saveHTOTAL_B;
+ u32 saveHBLANK_B;
+ u32 saveHSYNC_B;
+ u32 saveVTOTAL_B;
+ u32 saveVBLANK_B;
+ u32 saveVSYNC_B;
u32 saveBCLRPAT_B;
- u32 saveDSPBSTRIDE;
- u32 saveDSPBSIZE;
- u32 saveDSPBPOS;
- u32 saveDSPBBASE;
- u32 saveDSPBSURF;
+ u32 saveDSPBSTRIDE;
+ u32 saveDSPBSIZE;
+ u32 saveDSPBPOS;
+ u32 saveDSPBBASE;
+ u32 saveDSPBSURF;
u32 saveDSPBTILEOFF;
- u32 saveVCLK_DIVISOR_VGA0;
- u32 saveVCLK_DIVISOR_VGA1;
- u32 saveVCLK_POST_DIV;
- u32 saveVGACNTRL;
- u32 saveADPA;
- u32 saveLVDS;
+ u32 saveVCLK_DIVISOR_VGA0;
+ u32 saveVCLK_DIVISOR_VGA1;
+ u32 saveVCLK_POST_DIV;
+ u32 saveVGACNTRL;
+ u32 saveADPA;
+ u32 saveLVDS;
u32 saveLVDSPP_ON;
u32 saveLVDSPP_OFF;
- u32 saveDVOA;
- u32 saveDVOB;
- u32 saveDVOC;
- u32 savePP_ON;
- u32 savePP_OFF;
- u32 savePP_CONTROL;
- u32 savePP_CYCLE;
- u32 savePFIT_CONTROL;
- u32 save_palette_a[256];
- u32 save_palette_b[256];
+ u32 saveDVOA;
+ u32 saveDVOB;
+ u32 saveDVOC;
+ u32 savePP_ON;
+ u32 savePP_OFF;
+ u32 savePP_CONTROL;
+ u32 savePP_CYCLE;
+ u32 savePFIT_CONTROL;
+ u32 save_palette_a[256];
+ u32 save_palette_b[256];
u32 saveFBC_CFB_BASE;
u32 saveFBC_LL_BASE;
u32 saveFBC_CONTROL;
u32 saveFBC_CONTROL2;
- u32 saveSWF0[16];
- u32 saveSWF1[16];
- u32 saveSWF2[3];
+ u32 saveSWF0[16];
+ u32 saveSWF1[16];
+ u32 saveSWF2[3];
u8 saveMSR;
u8 saveSR[8];
u8 saveGR[24];
@@ -293,7 +293,7 @@ extern void i915_mem_release(struct drm_device * dev,
extern void i915_fence_handler(struct drm_device *dev);
extern int i915_fence_emit_sequence(struct drm_device *dev, uint32_t class,
uint32_t flags,
- uint32_t *sequence,
+ uint32_t *sequence,
uint32_t *native_type);
extern void i915_poke_flush(struct drm_device *dev, uint32_t class);
extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags);
@@ -309,7 +309,7 @@ extern int i915_init_mem_type(struct drm_device *dev, uint32_t type,
struct drm_mem_type_manager *man);
extern uint32_t i915_evict_mask(struct drm_buffer_object *bo);
extern int i915_move(struct drm_buffer_object *bo, int evict,
- int no_wait, struct drm_bo_mem_reg *new_mem);
+ int no_wait, struct drm_bo_mem_reg *new_mem);
void i915_flush_ttm(struct drm_ttm *ttm);
#endif
@@ -320,7 +320,7 @@ extern void intel_fini_chipset_flush_compat(struct drm_device *dev);
#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
-#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
+#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
#define I915_VERBOSE 0
@@ -401,7 +401,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define VGA_CR_INDEX_CGA 0x3d4
#define VGA_CR_DATA_CGA 0x3d5
-#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
+#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
#define CMD_REPORT_HEAD (7<<23)
#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
@@ -463,7 +463,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define I915REG_HWSTAM 0x02098
#define I915REG_INT_IDENTITY_R 0x020a4
-#define I915REG_INT_MASK_R 0x020a8
+#define I915REG_INT_MASK_R 0x020a8
#define I915REG_INT_ENABLE_R 0x020a0
#define I915REG_INSTPM 0x020c0
@@ -476,7 +476,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define SRX_INDEX 0x3c4
#define SRX_DATA 0x3c5
#define SR01 1
-#define SR01_SCREEN_OFF (1<<5)
+#define SR01_SCREEN_OFF (1<<5)
#define PPCR 0x61204
#define PPCR_ON (1<<0)
@@ -496,29 +496,29 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define ADPA_DPMS_OFF (3<<10)
#define NOPID 0x2094
-#define LP_RING 0x2030
-#define HP_RING 0x2040
+#define LP_RING 0x2030
+#define HP_RING 0x2040
/* The binner has its own ring buffer:
*/
#define HWB_RING 0x2400
-#define RING_TAIL 0x00
+#define RING_TAIL 0x00
#define TAIL_ADDR 0x001FFFF8
-#define RING_HEAD 0x04
-#define HEAD_WRAP_COUNT 0xFFE00000
-#define HEAD_WRAP_ONE 0x00200000
-#define HEAD_ADDR 0x001FFFFC
-#define RING_START 0x08
-#define START_ADDR 0x0xFFFFF000
-#define RING_LEN 0x0C
-#define RING_NR_PAGES 0x001FF000
-#define RING_REPORT_MASK 0x00000006
-#define RING_REPORT_64K 0x00000002
-#define RING_REPORT_128K 0x00000004
-#define RING_NO_REPORT 0x00000000
-#define RING_VALID_MASK 0x00000001
-#define RING_VALID 0x00000001
-#define RING_INVALID 0x00000000
+#define RING_HEAD 0x04
+#define HEAD_WRAP_COUNT 0xFFE00000
+#define HEAD_WRAP_ONE 0x00200000
+#define HEAD_ADDR 0x001FFFFC
+#define RING_START 0x08
+#define START_ADDR 0x0xFFFFF000
+#define RING_LEN 0x0C
+#define RING_NR_PAGES 0x001FF000
+#define RING_REPORT_MASK 0x00000006
+#define RING_REPORT_64K 0x00000002
+#define RING_REPORT_128K 0x00000004
+#define RING_NO_REPORT 0x00000000
+#define RING_VALID_MASK 0x00000001
+#define RING_VALID 0x00000001
+#define RING_INVALID 0x00000000
/* Instruction parser error reg:
*/
@@ -536,7 +536,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
*/
#define DMA_FADD_S 0x20d4
-/* Cache mode 0 reg.
+/* Cache mode 0 reg.
* - Manipulating render cache behaviour is central
* to the concept of zone rendering, tuning this reg can help avoid
* unnecessary render cache reads and even writes (for z/stencil)
@@ -565,7 +565,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define BINCTL 0x2420
#define BC_MASK (1 << 9)
-/* Binned scene info.
+/* Binned scene info.
*/
#define BINSCENE 0x2428
#define BS_OP_LOAD (1 << 8)
@@ -583,7 +583,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
*/
#define BDCD 0x2488
-/* Binner pointer cache debug reg:
+/* Binner pointer cache debug reg:
*/
#define BPCD 0x248c
@@ -640,9 +640,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
-#define MI_BATCH_BUFFER ((0x30<<23)|1)
-#define MI_BATCH_BUFFER_START (0x31<<23)
-#define MI_BATCH_BUFFER_END (0xA<<23)
+#define MI_BATCH_BUFFER ((0x30<<23)|1)
+#define MI_BATCH_BUFFER_START (0x31<<23)
+#define MI_BATCH_BUFFER_END (0xA<<23)
#define MI_BATCH_NON_SECURE (1)
#define MI_BATCH_NON_SECURE_I965 (1<<8)
@@ -738,20 +738,20 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
/* I830 CRTC registers */
#define HTOTAL_A 0x60000
#define HBLANK_A 0x60004
-#define HSYNC_A 0x60008
+#define HSYNC_A 0x60008
#define VTOTAL_A 0x6000c
#define VBLANK_A 0x60010
-#define VSYNC_A 0x60014
+#define VSYNC_A 0x60014
#define PIPEASRC 0x6001c
#define BCLRPAT_A 0x60020
#define VSYNCSHIFT_A 0x60028
#define HTOTAL_B 0x61000
#define HBLANK_B 0x61004
-#define HSYNC_B 0x61008
+#define HSYNC_B 0x61008
#define VTOTAL_B 0x6100c
#define VBLANK_B 0x61010
-#define VSYNC_B 0x61014
+#define VSYNC_B 0x61014
#define PIPEBSRC 0x6101c
#define BCLRPAT_B 0x61020
#define VSYNCSHIFT_B 0x61028
@@ -886,7 +886,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
*/
# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
-/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
+/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
* This best be set to the default value (3) or the CRT won't work. No,
* I don't entirely understand what this does...
*/
@@ -907,7 +907,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
#define ADPA 0x61100
-#define ADPA_DAC_ENABLE (1<<31)
+#define ADPA_DAC_ENABLE (1<<31)
#define ADPA_DAC_DISABLE 0
#define ADPA_PIPE_SELECT_MASK (1<<30)
#define ADPA_PIPE_A_SELECT 0
@@ -1037,7 +1037,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define PIPEACONF_PIPE_UNLOCKED 0
#define PIPEACONF_PIPE_LOCKED (1<<25)
#define PIPEACONF_PALETTE 0
-#define PIPEACONF_GAMMA (1<<24)
+#define PIPEACONF_GAMMA (1<<24)
#define PIPECONF_FORCE_BORDER (1<<25)
#define PIPECONF_PROGRESSIVE (0 << 21)
#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
@@ -1048,7 +1048,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define PIPEBCONF_DISABLE 0
#define PIPEBCONF_DOUBLE_WIDE (1<<30)
#define PIPEBCONF_DISABLE 0
-#define PIPEBCONF_GAMMA (1<<24)
+#define PIPEBCONF_GAMMA (1<<24)
#define PIPEBCONF_PALETTE 0
#define PIPEBGCMAXRED 0x71010
@@ -1060,7 +1060,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define DSPACNTR 0x70180
#define DSPBCNTR 0x71180
-#define DISPLAY_PLANE_ENABLE (1<<31)
+#define DISPLAY_PLANE_ENABLE (1<<31)
#define DISPLAY_PLANE_DISABLE 0
#define DISPPLANE_GAMMA_ENABLE (1<<30)
#define DISPPLANE_GAMMA_DISABLE 0
@@ -1068,7 +1068,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define DISPPLANE_8BPP (0x2<<26)
#define DISPPLANE_15_16BPP (0x4<<26)
#define DISPPLANE_16BPP (0x5<<26)
-#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
+#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
#define DISPPLANE_32BPP (0x7<<26)
#define DISPPLANE_STEREO_ENABLE (1<<25)
#define DISPPLANE_STEREO_DISABLE 0
@@ -1169,7 +1169,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
- (dev)->pci_device == 0x29B2 || \
+ (dev)->pci_device == 0x29B2 || \
(dev)->pci_device == 0x29D2)
#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c
index db18a895..43e73e06 100644
--- a/shared-core/i915_irq.c
+++ b/shared-core/i915_irq.c
@@ -3,7 +3,7 @@
/*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
@@ -11,11 +11,11 @@
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
@@ -23,7 +23,7 @@
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
+ *
*/
#include "drmP.h"
@@ -310,7 +310,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
pipea_stats = I915_READ(I915REG_PIPEASTAT);
pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
-
+
temp = I915_READ16(I915REG_INT_IDENTITY_R);
temp &= (dev_priv->irq_enable_reg | USER_INT_FLAG);
@@ -354,7 +354,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
if (dev_priv->swaps_pending > 0)
drm_locked_tasklet(dev, i915_vblank_tasklet);
- I915_WRITE(I915REG_PIPEASTAT,
+ I915_WRITE(I915REG_PIPEASTAT,
pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
I915_VBLANK_CLEAR);
I915_WRITE(I915REG_PIPEBSTAT,
@@ -367,7 +367,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
int i915_emit_irq(struct drm_device * dev)
{
-
+
drm_i915_private_t *dev_priv = dev->dev_private;
RING_LOCALS;
@@ -397,7 +397,7 @@ void i915_user_irq_on(drm_i915_private_t *dev_priv)
DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
}
-
+
void i915_user_irq_off(drm_i915_private_t *dev_priv)
{
DRM_SPINLOCK(&dev_priv->user_irq_lock);
@@ -407,7 +407,7 @@ void i915_user_irq_off(drm_i915_private_t *dev_priv)
}
DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
}
-
+
static int i915_wait_irq(struct drm_device * dev, int irq_nr)
{
@@ -421,7 +421,7 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
return 0;
dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
-
+
i915_user_irq_on(dev_priv);
DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
READ_BREADCRUMB(dev_priv) >= irq_nr);
@@ -453,7 +453,7 @@ static int i915_driver_vblank_do_wait(struct drm_device *dev,
DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
(((cur_vblank = atomic_read(counter))
- *sequence) <= (1<<23)));
-
+
*sequence = cur_vblank;
return ret;
@@ -513,8 +513,8 @@ int i915_irq_wait(struct drm_device *dev, void *data,
static void i915_enable_interrupt (struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-
- dev_priv->irq_enable_reg = USER_INT_FLAG;
+
+ dev_priv->irq_enable_reg = USER_INT_FLAG;
if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
dev_priv->irq_enable_reg |= VSYNC_PIPEA_FLAG;
if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
@@ -538,7 +538,7 @@ int i915_vblank_pipe_set(struct drm_device *dev, void *data,
}
if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
- DRM_ERROR("%s called with invalid pipe 0x%x\n",
+ DRM_ERROR("%s called with invalid pipe 0x%x\n",
__FUNCTION__, pipe->pipe);
return -EINVAL;
}
diff --git a/shared-core/i915_mem.c b/shared-core/i915_mem.c
index 5bf29a1e..d360896f 100644
--- a/shared-core/i915_mem.c
+++ b/shared-core/i915_mem.c
@@ -375,7 +375,7 @@ int i915_mem_destroy_heap( struct drm_device *dev, void *data,
DRM_ERROR("get_heap failed");
return -EFAULT;
}
-
+
if (!*heap) {
DRM_ERROR("heap not initialized?");
return -EFAULT;
diff --git a/shared-core/mach64_dma.c b/shared-core/mach64_dma.c
index e0a67458..13fa0446 100644
--- a/shared-core/mach64_dma.c
+++ b/shared-core/mach64_dma.c
@@ -53,7 +53,7 @@
*
* \param dev_priv pointer to device private data structure.
* \param entries number of free entries in the FIFO to wait for.
- *
+ *
* \returns zero on success, or -EBUSY if the timeout (specificed by
* drm_mach64_private::usec_timeout) occurs.
*/
@@ -107,10 +107,10 @@ int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv)
*
* This function should be called before writing new entries to the ring
* buffer.
- *
+ *
* \param dev_priv pointer to device private data structure.
* \param n number of free entries in the ring buffer to wait for.
- *
+ *
* \returns zero on success, or -EBUSY if the timeout (specificed by
* drm_mach64_private_t::usec_timeout) occurs.
*
@@ -139,7 +139,7 @@ int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n)
}
/**
- * Wait until all DMA requests have been processed...
+ * Wait until all DMA requests have been processed...
*
* \sa mach64_wait_ring()
*/
diff --git a/shared-core/mach64_drv.h b/shared-core/mach64_drv.h
index cebd4c6e..79c2c61d 100644
--- a/shared-core/mach64_drv.h
+++ b/shared-core/mach64_drv.h
@@ -171,14 +171,14 @@ extern void mach64_driver_irq_uninstall(struct drm_device * dev);
#define MACH64_AGP_CNTL 0x014c
#define MACH64_ALPHA_TST_CNTL 0x0550
-#define MACH64_DSP_CONFIG 0x0420
-#define MACH64_DSP_ON_OFF 0x0424
-#define MACH64_EXT_MEM_CNTL 0x04ac
-#define MACH64_GEN_TEST_CNTL 0x04d0
-#define MACH64_HW_DEBUG 0x047c
-#define MACH64_MEM_ADDR_CONFIG 0x0434
-#define MACH64_MEM_BUF_CNTL 0x042c
-#define MACH64_MEM_CNTL 0x04b0
+#define MACH64_DSP_CONFIG 0x0420
+#define MACH64_DSP_ON_OFF 0x0424
+#define MACH64_EXT_MEM_CNTL 0x04ac
+#define MACH64_GEN_TEST_CNTL 0x04d0
+#define MACH64_HW_DEBUG 0x047c
+#define MACH64_MEM_ADDR_CONFIG 0x0434
+#define MACH64_MEM_BUF_CNTL 0x042c
+#define MACH64_MEM_CNTL 0x04b0
#define MACH64_BM_ADDR 0x0648
#define MACH64_BM_COMMAND 0x0188
@@ -205,16 +205,16 @@ extern void mach64_driver_irq_uninstall(struct drm_device * dev);
#define MACH64_CLR_CMP_CLR 0x0700
#define MACH64_CLR_CMP_CNTL 0x0708
#define MACH64_CLR_CMP_MASK 0x0704
-#define MACH64_CONFIG_CHIP_ID 0x04e0
-#define MACH64_CONFIG_CNTL 0x04dc
-#define MACH64_CONFIG_STAT0 0x04e4
-#define MACH64_CONFIG_STAT1 0x0494
-#define MACH64_CONFIG_STAT2 0x0498
+#define MACH64_CONFIG_CHIP_ID 0x04e0
+#define MACH64_CONFIG_CNTL 0x04dc
+#define MACH64_CONFIG_STAT0 0x04e4
+#define MACH64_CONFIG_STAT1 0x0494
+#define MACH64_CONFIG_STAT2 0x0498
#define MACH64_CONTEXT_LOAD_CNTL 0x072c
#define MACH64_CONTEXT_MASK 0x0720
#define MACH64_COMPOSITE_SHADOW_ID 0x0798
-#define MACH64_CRC_SIG 0x04e8
-#define MACH64_CUSTOM_MACRO_CNTL 0x04d4
+#define MACH64_CRC_SIG 0x04e8
+#define MACH64_CUSTOM_MACRO_CNTL 0x04d4
#define MACH64_DP_BKGD_CLR 0x06c0
#define MACH64_DP_FOG_CLR 0x06c4
@@ -358,7 +358,7 @@ extern void mach64_driver_irq_uninstall(struct drm_device * dev);
#define MACH64_TEX_0_OFF 0x05c0
#define MACH64_TEX_CNTL 0x0774
#define MACH64_TEX_SIZE_PITCH 0x0770
-#define MACH64_TIMER_CONFIG 0x0428
+#define MACH64_TIMER_CONFIG 0x0428
#define MACH64_VERTEX_1_ARGB 0x0254
#define MACH64_VERTEX_1_S 0x0240
@@ -758,7 +758,7 @@ mach64_update_ring_snapshot(drm_mach64_private_t * dev_priv)
#define RING_WRITE_OFS _ring_write
-#define BEGIN_RING( n ) \
+#define BEGIN_RING( n ) \
do { \
if ( MACH64_VERBOSE ) { \
DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
@@ -789,7 +789,7 @@ do { \
_ring_write &= _ring_mask; \
} while (0)
-#define ADVANCE_RING() \
+#define ADVANCE_RING() \
do { \
if ( MACH64_VERBOSE ) { \
DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
@@ -808,12 +808,12 @@ do { \
#define DMALOCALS \
drm_mach64_freelist_t *_entry = NULL; \
- struct drm_buf *_buf = NULL; \
+ struct drm_buf *_buf = NULL; \
u32 *_buf_wptr; int _outcount
#define GETBUFPTR( __buf ) \
-((dev_priv->is_pci) ? \
- ((u32 *)(__buf)->address) : \
+((dev_priv->is_pci) ? \
+ ((u32 *)(__buf)->address) : \
((u32 *)((char *)dev_priv->dev_buffers->handle + (__buf)->offset)))
#define GETBUFADDR( __buf ) ((u32)(__buf)->bus_address)
@@ -844,7 +844,7 @@ static __inline__ int mach64_find_pending_buf_entry(drm_mach64_private_t *
return 0;
}
-#define DMASETPTR( _p ) \
+#define DMASETPTR( _p ) \
do { \
_buf = (_p); \
_outcount = 0; \
@@ -913,10 +913,10 @@ do { \
__FUNCTION__, _buf->idx ); \
return -EFAULT; \
} \
- } else { \
+ } else { \
if (list_empty(&dev_priv->placeholders)) { \
DRM_ERROR( "DMAADVANCE() in %s: empty placeholder list\n", \
- __FUNCTION__ ); \
+ __FUNCTION__ ); \
return -EFAULT; \
} \
ptr = dev_priv->placeholders.next; \
diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c
index a86dd31c..44b14945 100644
--- a/shared-core/mga_dma.c
+++ b/shared-core/mga_dma.c
@@ -28,7 +28,7 @@
/**
* \file mga_dma.c
* DMA support for MGA G200 / G400.
- *
+ *
* \author Rickard E. (Rik) Faith <faith@valinux.com>
* \author Jeff Hartmann <jhartmann@valinux.com>
* \author Keith Whitwell <keith@tungstengraphics.com>
@@ -420,7 +420,7 @@ int mga_driver_load(struct drm_device *dev, unsigned long flags)
/**
* Bootstrap the driver for AGP DMA.
- *
+ *
* \todo
* Investigate whether there is any benifit to storing the WARP microcode in
* AGP memory. If not, the microcode may as well always be put in PCI
@@ -591,7 +591,7 @@ static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
/**
* Bootstrap the driver for PCI DMA.
- *
+ *
* \todo
* The algorithm for decreasing the size of the primary DMA buffer could be
* better. The size should be rounded up to the nearest page size, then
@@ -600,7 +600,7 @@ static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
* \todo
* Determine whether the maximum address passed to drm_pci_alloc is correct.
* The same goes for drm_addbufs_pci.
- *
+ *
* \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
*/
static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
@@ -613,7 +613,7 @@ static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
int err;
struct drm_buf_desc req;
-
+
if (dev->dma == NULL) {
DRM_ERROR("dev->dma is NULL\n");
return -EFAULT;
@@ -656,13 +656,13 @@ static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
if (dev_priv->primary->size != dma_bs->primary_size) {
DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
- dma_bs->primary_size,
+ dma_bs->primary_size,
(unsigned) dev_priv->primary->size);
dma_bs->primary_size = dev_priv->primary->size;
}
for ( bin_count = dma_bs->secondary_bin_count
- ; bin_count > 0
+ ; bin_count > 0
; bin_count-- ) {
(void) memset( &req, 0, sizeof(req) );
req.count = bin_count;
@@ -673,7 +673,7 @@ static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
break;
}
}
-
+
if (bin_count == 0) {
DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
return err;
@@ -736,7 +736,7 @@ static int mga_do_dma_bootstrap(struct drm_device * dev,
if (is_agp) {
err = mga_do_agp_dma_bootstrap(dev, dma_bs);
}
-
+
/* If we attempted to initialize the card for AGP DMA but failed,
* clean-up any mess that may have been created.
*/
@@ -768,7 +768,7 @@ int mga_dma_bootstrap(struct drm_device *dev, void *data,
drm_mga_dma_bootstrap_t *bootstrap = data;
int err;
static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
- const drm_mga_private_t * const dev_priv =
+ const drm_mga_private_t * const dev_priv =
(drm_mga_private_t *) dev->dev_private;
@@ -951,7 +951,7 @@ static int mga_do_cleanup_dma(struct drm_device * dev, int full_cleanup)
&& (dev_priv->warp->type != _DRM_CONSISTENT))
drm_core_ioremapfree(dev_priv->warp, dev);
- if ((dev_priv->primary != NULL)
+ if ((dev_priv->primary != NULL)
&& (dev_priv->primary->type != _DRM_CONSISTENT))
drm_core_ioremapfree(dev_priv->primary, dev);
diff --git a/shared-core/mga_drm.h b/shared-core/mga_drm.h
index 15c2dea2..c03d3220 100644
--- a/shared-core/mga_drm.h
+++ b/shared-core/mga_drm.h
@@ -302,10 +302,10 @@ typedef struct drm_mga_init {
typedef struct drm_mga_dma_bootstrap {
/**
* \name AGP texture region
- *
+ *
* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
* be filled in with the actual AGP texture settings.
- *
+ *
* \warning
* If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
* is zero, it means that PCI memory (most likely through the use of
@@ -319,7 +319,7 @@ typedef struct drm_mga_dma_bootstrap {
/**
* Requested size of the primary DMA region.
- *
+ *
* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
* filled in with the actual AGP mode. If AGP was not available
*/
@@ -328,18 +328,18 @@ typedef struct drm_mga_dma_bootstrap {
/**
* Requested number of secondary DMA buffers.
- *
+ *
* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
* filled in with the actual number of secondary DMA buffers
* allocated. Particularly when PCI DMA is used, this may be
* (subtantially) less than the number requested.
*/
uint32_t secondary_bin_count;
-
-
+
+
/**
* Requested size of each secondary DMA buffer.
- *
+ *
* While the kernel \b is free to reduce
* dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
* to reduce dma_mga_dma_bootstrap::secondary_bin_size.
@@ -352,7 +352,7 @@ typedef struct drm_mga_dma_bootstrap {
* \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
* zero, it means that PCI DMA should be used, even if AGP is
* possible.
- *
+ *
* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
* filled in with the actual AGP mode. If AGP was not available
* (i.e., PCI DMA was used), this value will be zero.
diff --git a/shared-core/mga_drv.h b/shared-core/mga_drv.h
index 8254c3f1..0c7fab5b 100644
--- a/shared-core/mga_drv.h
+++ b/shared-core/mga_drv.h
@@ -109,7 +109,7 @@ typedef struct drm_mga_private {
/**
* \name MMIO region parameters.
- *
+ *
* \sa drm_mga_private_t::mmio
*/
/*@{*/
@@ -143,7 +143,7 @@ typedef struct drm_mga_private {
drm_local_map_t *warp;
drm_local_map_t *primary;
drm_local_map_t *agp_textures;
-
+
unsigned long agp_handle;
unsigned int agp_size;
} drm_mga_private_t;
@@ -216,8 +216,8 @@ static inline u32 _MGA_READ(u32 * addr)
#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val))
#endif
-#define DWGREG0 0x1c00
-#define DWGREG0_END 0x1dff
+#define DWGREG0 0x1c00
+#define DWGREG0_END 0x1dff
#define DWGREG1 0x2c00
#define DWGREG1_END 0x2dff
@@ -394,22 +394,22 @@ do { \
#define MGA_VINTCLR (1 << 4)
#define MGA_VINTEN (1 << 5)
-#define MGA_ALPHACTRL 0x2c7c
-#define MGA_AR0 0x1c60
-#define MGA_AR1 0x1c64
-#define MGA_AR2 0x1c68
-#define MGA_AR3 0x1c6c
-#define MGA_AR4 0x1c70
-#define MGA_AR5 0x1c74
-#define MGA_AR6 0x1c78
+#define MGA_ALPHACTRL 0x2c7c
+#define MGA_AR0 0x1c60
+#define MGA_AR1 0x1c64
+#define MGA_AR2 0x1c68
+#define MGA_AR3 0x1c6c
+#define MGA_AR4 0x1c70
+#define MGA_AR5 0x1c74
+#define MGA_AR6 0x1c78
#define MGA_CXBNDRY 0x1c80
-#define MGA_CXLEFT 0x1ca0
+#define MGA_CXLEFT 0x1ca0
#define MGA_CXRIGHT 0x1ca4
-#define MGA_DMAPAD 0x1c54
-#define MGA_DSTORG 0x2cb8
-#define MGA_DWGCTL 0x1c00
+#define MGA_DMAPAD 0x1c54
+#define MGA_DSTORG 0x2cb8
+#define MGA_DWGCTL 0x1c00
# define MGA_OPCOD_MASK (15 << 0)
# define MGA_OPCOD_TRAP (4 << 0)
# define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
@@ -455,27 +455,27 @@ do { \
# define MGA_CLIPDIS (1 << 31)
#define MGA_DWGSYNC 0x2c4c
-#define MGA_FCOL 0x1c24
-#define MGA_FIFOSTATUS 0x1e10
-#define MGA_FOGCOL 0x1cf4
+#define MGA_FCOL 0x1c24
+#define MGA_FIFOSTATUS 0x1e10
+#define MGA_FOGCOL 0x1cf4
#define MGA_FXBNDRY 0x1c84
-#define MGA_FXLEFT 0x1ca8
+#define MGA_FXLEFT 0x1ca8
#define MGA_FXRIGHT 0x1cac
-#define MGA_ICLEAR 0x1e18
+#define MGA_ICLEAR 0x1e18
# define MGA_SOFTRAPICLR (1 << 0)
# define MGA_VLINEICLR (1 << 5)
-#define MGA_IEN 0x1e1c
+#define MGA_IEN 0x1e1c
# define MGA_SOFTRAPIEN (1 << 0)
# define MGA_VLINEIEN (1 << 5)
-#define MGA_LEN 0x1c5c
+#define MGA_LEN 0x1c5c
#define MGA_MACCESS 0x1c04
-#define MGA_PITCH 0x1c8c
-#define MGA_PLNWT 0x1c1c
-#define MGA_PRIMADDRESS 0x1e58
+#define MGA_PITCH 0x1c8c
+#define MGA_PLNWT 0x1c1c
+#define MGA_PRIMADDRESS 0x1e58
# define MGA_DMA_GENERAL (0 << 0)
# define MGA_DMA_BLIT (1 << 0)
# define MGA_DMA_VECTOR (2 << 0)
@@ -487,43 +487,43 @@ do { \
# define MGA_PRIMPTREN0 (1 << 0)
# define MGA_PRIMPTREN1 (1 << 1)
-#define MGA_RST 0x1e40
+#define MGA_RST 0x1e40
# define MGA_SOFTRESET (1 << 0)
# define MGA_SOFTEXTRST (1 << 1)
-#define MGA_SECADDRESS 0x2c40
-#define MGA_SECEND 0x2c44
-#define MGA_SETUPADDRESS 0x2cd0
-#define MGA_SETUPEND 0x2cd4
+#define MGA_SECADDRESS 0x2c40
+#define MGA_SECEND 0x2c44
+#define MGA_SETUPADDRESS 0x2cd0
+#define MGA_SETUPEND 0x2cd4
#define MGA_SGN 0x1c58
#define MGA_SOFTRAP 0x2c48
-#define MGA_SRCORG 0x2cb4
+#define MGA_SRCORG 0x2cb4
# define MGA_SRMMAP_MASK (1 << 0)
# define MGA_SRCMAP_FB (0 << 0)
# define MGA_SRCMAP_SYSMEM (1 << 0)
# define MGA_SRCACC_MASK (1 << 1)
# define MGA_SRCACC_PCI (0 << 1)
# define MGA_SRCACC_AGP (1 << 1)
-#define MGA_STATUS 0x1e14
+#define MGA_STATUS 0x1e14
# define MGA_SOFTRAPEN (1 << 0)
# define MGA_VSYNCPEN (1 << 4)
# define MGA_VLINEPEN (1 << 5)
# define MGA_DWGENGSTS (1 << 16)
# define MGA_ENDPRDMASTS (1 << 17)
#define MGA_STENCIL 0x2cc8
-#define MGA_STENCILCTL 0x2ccc
+#define MGA_STENCILCTL 0x2ccc
-#define MGA_TDUALSTAGE0 0x2cf8
-#define MGA_TDUALSTAGE1 0x2cfc
-#define MGA_TEXBORDERCOL 0x2c5c
-#define MGA_TEXCTL 0x2c30
+#define MGA_TDUALSTAGE0 0x2cf8
+#define MGA_TDUALSTAGE1 0x2cfc
+#define MGA_TEXBORDERCOL 0x2c5c
+#define MGA_TEXCTL 0x2c30
#define MGA_TEXCTL2 0x2c3c
# define MGA_DUALTEX (1 << 7)
# define MGA_G400_TC2_MAGIC (1 << 15)
# define MGA_MAP1_ENABLE (1 << 31)
-#define MGA_TEXFILTER 0x2c58
-#define MGA_TEXHEIGHT 0x2c2c
-#define MGA_TEXORG 0x2c24
+#define MGA_TEXFILTER 0x2c58
+#define MGA_TEXHEIGHT 0x2c2c
+#define MGA_TEXORG 0x2c24
# define MGA_TEXORGMAP_MASK (1 << 0)
# define MGA_TEXORGMAP_FB (0 << 0)
# define MGA_TEXORGMAP_SYSMEM (1 << 0)
@@ -534,45 +534,45 @@ do { \
#define MGA_TEXORG2 0x2ca8
#define MGA_TEXORG3 0x2cac
#define MGA_TEXORG4 0x2cb0
-#define MGA_TEXTRANS 0x2c34
-#define MGA_TEXTRANSHIGH 0x2c38
-#define MGA_TEXWIDTH 0x2c28
-
-#define MGA_WACCEPTSEQ 0x1dd4
-#define MGA_WCODEADDR 0x1e6c
-#define MGA_WFLAG 0x1dc4
-#define MGA_WFLAG1 0x1de0
+#define MGA_TEXTRANS 0x2c34
+#define MGA_TEXTRANSHIGH 0x2c38
+#define MGA_TEXWIDTH 0x2c28
+
+#define MGA_WACCEPTSEQ 0x1dd4
+#define MGA_WCODEADDR 0x1e6c
+#define MGA_WFLAG 0x1dc4
+#define MGA_WFLAG1 0x1de0
#define MGA_WFLAGNB 0x1e64
-#define MGA_WFLAGNB1 0x1e08
+#define MGA_WFLAGNB1 0x1e08
#define MGA_WGETMSB 0x1dc8
-#define MGA_WIADDR 0x1dc0
+#define MGA_WIADDR 0x1dc0
#define MGA_WIADDR2 0x1dd8
# define MGA_WMODE_SUSPEND (0 << 0)
# define MGA_WMODE_RESUME (1 << 0)
# define MGA_WMODE_JUMP (2 << 0)
# define MGA_WMODE_START (3 << 0)
# define MGA_WAGP_ENABLE (1 << 2)
-#define MGA_WMISC 0x1e70
+#define MGA_WMISC 0x1e70
# define MGA_WUCODECACHE_ENABLE (1 << 0)
# define MGA_WMASTER_ENABLE (1 << 1)
# define MGA_WCACHEFLUSH_ENABLE (1 << 3)
#define MGA_WVRTXSZ 0x1dcc
-#define MGA_YBOT 0x1c9c
-#define MGA_YDST 0x1c90
+#define MGA_YBOT 0x1c9c
+#define MGA_YDST 0x1c90
#define MGA_YDSTLEN 0x1c88
#define MGA_YDSTORG 0x1c94
-#define MGA_YTOP 0x1c98
+#define MGA_YTOP 0x1c98
-#define MGA_ZORG 0x1c0c
+#define MGA_ZORG 0x1c0c
/* This finishes the current batch of commands
*/
-#define MGA_EXEC 0x0100
+#define MGA_EXEC 0x0100
/* AGP PLL encoding (for G200 only).
*/
-#define MGA_AGP_PLL 0x1e4c
+#define MGA_AGP_PLL 0x1e4c
# define MGA_AGP2XPLL_DISABLE (0 << 0)
# define MGA_AGP2XPLL_ENABLE (1 << 0)
diff --git a/shared-core/mga_irq.c b/shared-core/mga_irq.c
index 8b555e2e..c18bae9f 100644
--- a/shared-core/mga_irq.c
+++ b/shared-core/mga_irq.c
@@ -145,6 +145,6 @@ void mga_driver_irq_uninstall(struct drm_device * dev)
/* Disable *all* interrupts */
MGA_WRITE(MGA_IEN, 0);
-
+
dev->irq_enabled = 0;
}
diff --git a/shared-core/mga_state.c b/shared-core/mga_state.c
index 70b7caa0..0b8ba048 100644
--- a/shared-core/mga_state.c
+++ b/shared-core/mga_state.c
@@ -162,8 +162,8 @@ static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
DMA_LOCALS;
-/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
-/* tex->texctl, tex->texctl2); */
+/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
+/* tex->texctl, tex->texctl2); */
BEGIN_DMA(6);
@@ -206,8 +206,8 @@ static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
DMA_LOCALS;
-/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
-/* tex->texctl, tex->texctl2); */
+/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
+/* tex->texctl, tex->texctl2); */
BEGIN_DMA(5);
@@ -276,7 +276,7 @@ static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
unsigned int pipe = sarea_priv->warp_pipe;
DMA_LOCALS;
-/* printk("mga_g400_emit_pipe %x\n", pipe); */
+/* printk("mga_g400_emit_pipe %x\n", pipe); */
BEGIN_DMA(10);
diff --git a/shared-core/nouveau_dma.c b/shared-core/nouveau_dma.c
index b33df588..b406c22d 100644
--- a/shared-core/nouveau_dma.c
+++ b/shared-core/nouveau_dma.c
@@ -177,4 +177,3 @@ nouveau_dma_wait(struct drm_device *dev, int size)
return 0;
}
-
diff --git a/shared-core/nouveau_dma.h b/shared-core/nouveau_dma.h
index 5e51c1c4..f8df54eb 100644
--- a/shared-core/nouveau_dma.h
+++ b/shared-core/nouveau_dma.h
@@ -95,4 +95,3 @@ typedef enum {
} while(0)
#endif
-
diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h
index 988d467a..3bf40089 100644
--- a/shared-core/nouveau_drm.h
+++ b/shared-core/nouveau_drm.h
@@ -158,4 +158,3 @@ struct drm_nouveau_sarea {
#define DRM_NOUVEAU_MEM_FREE 0x09
#endif /* __NOUVEAU_DRM_H__ */
-
diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h
index b881bead..8b00726b 100644
--- a/shared-core/nouveau_drv.h
+++ b/shared-core/nouveau_drv.h
@@ -59,7 +59,7 @@ enum nouveau_flags {
};
#define NVOBJ_ENGINE_SW 0
-#define NVOBJ_ENGINE_GR 1
+#define NVOBJ_ENGINE_GR 1
#define NVOBJ_ENGINE_INT 0xdeadbeef
#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
@@ -587,4 +587,3 @@ extern void nouveau_fence_handler(struct drm_device *dev, int channel);
#define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
#endif /* __NOUVEAU_DRV_H__ */
-
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index f82d130b..e2cb209c 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -1,4 +1,4 @@
-/*
+/*
* Copyright 2005-2006 Stephane Marchesin
* All Rights Reserved.
*
@@ -63,7 +63,7 @@ int nouveau_fifo_ctx_size(struct drm_device *dev)
/* voir nv_xaa.c : NVResetGraphics
* mémoire mappée par nv_driver.c : NVMapMem
- * voir nv_driver.c : NVPreInit
+ * voir nv_driver.c : NVPreInit
*/
static int nouveau_fifo_instmem_configure(struct drm_device *dev)
@@ -71,7 +71,7 @@ static int nouveau_fifo_instmem_configure(struct drm_device *dev)
struct drm_nouveau_private *dev_priv = dev->dev_private;
NV_WRITE(NV03_PFIFO_RAMHT,
- (0x03 << 24) /* search 128 */ |
+ (0x03 << 24) /* search 128 */ |
((dev_priv->ramht_bits - 9) << 16) |
(dev_priv->ramht_offset >> 8)
);
@@ -166,7 +166,7 @@ int nouveau_fifo_init(struct drm_device *dev)
NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACHE1_BIG_ENDIAN |
-#endif
+#endif
0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
@@ -282,9 +282,9 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
/*
* Alright, here is the full story
- * Nvidia cards have multiple hw fifo contexts (praise them for that,
+ * Nvidia cards have multiple hw fifo contexts (praise them for that,
* no complicated crash-prone context switches)
- * We allocate a new context for each app and let it write to it directly
+ * We allocate a new context for each app and let it write to it directly
* (woo, full userspace command submission !)
* When there are no more contexts, you lost
*/
diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c
index 08bd1da0..43f37ca0 100644
--- a/shared-core/nouveau_irq.c
+++ b/shared-core/nouveau_irq.c
@@ -82,7 +82,7 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
if (status & NV_PFIFO_INTR_CACHE_ERROR) {
uint32_t mthd, data;
int ptr;
-
+
ptr = get >> 2;
if (dev_priv->card_type < NV_40) {
mthd = NV_READ(NV04_PFIFO_CACHE1_METHOD(ptr));
@@ -366,7 +366,7 @@ nouveau_pgraph_intr_context_switch(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t chid;
-
+
chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1);
DRM_DEBUG("PGRAPH context switch interrupt channel %x\n", chid);
@@ -474,4 +474,3 @@ nouveau_irq_handler(DRM_IRQ_ARGS)
return IRQ_HANDLED;
}
-
diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c
index eb97a1c7..5259ea27 100644
--- a/shared-core/nouveau_mem.c
+++ b/shared-core/nouveau_mem.c
@@ -159,7 +159,7 @@ int nouveau_mem_init_heap(struct mem_block **heap, uint64_t start,
return 0;
}
-/*
+/*
* Free all blocks associated with the releasing file_priv
*/
void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap)
@@ -189,7 +189,7 @@ void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap)
}
}
-/*
+/*
* Cleanup everything
*/
void nouveau_mem_takedown(struct mem_block **heap)
@@ -288,7 +288,7 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev)
} else {
uint64_t mem;
- mem = (NV_READ(NV04_FIFO_DATA) &
+ mem = (NV_READ(NV04_FIFO_DATA) &
NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >>
NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT;
return mem*1024*1024;
@@ -448,7 +448,7 @@ int nouveau_mem_init(struct drm_device *dev)
DRM_DEBUG("Available VRAM: %dKiB\n", fb_size>>10);
if (fb_size>256*1024*1024) {
- /* On cards with > 256Mb, you can't map everything.
+ /* On cards with > 256Mb, you can't map everything.
* So we create a second FB heap for that type of memory */
if (nouveau_mem_init_heap(&dev_priv->fb_heap,
0, 256*1024*1024))
@@ -477,7 +477,7 @@ int nouveau_mem_init(struct drm_device *dev)
if (!ret) {
ret = nouveau_sgdma_nottm_hack_init(dev);
if (ret)
- nouveau_sgdma_takedown(dev);
+ nouveau_sgdma_takedown(dev);
}
if (ret)
@@ -489,7 +489,7 @@ int nouveau_mem_init(struct drm_device *dev)
0, dev_priv->gart_info.aper_size)) {
if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) {
nouveau_sgdma_nottm_hack_takedown(dev);
- nouveau_sgdma_takedown(dev);
+ nouveau_sgdma_takedown(dev);
}
}
}
@@ -507,7 +507,7 @@ int nouveau_mem_init(struct drm_device *dev)
} else {
if (nouveau_mem_init_heap(&dev_priv->pci_heap, 0,
dev->sg->pages * PAGE_SIZE)) {
- DRM_ERROR("Unable to initialize pci_heap!");
+ DRM_ERROR("Unable to initialize pci_heap!");
}
}
}
@@ -523,8 +523,8 @@ struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment,
int type;
struct drm_nouveau_private *dev_priv = dev->dev_private;
- /*
- * Make things easier on ourselves: all allocations are page-aligned.
+ /*
+ * Make things easier on ourselves: all allocations are page-aligned.
* We need that to map allocated regions into the user space
*/
if (alignment < PAGE_SHIFT)
@@ -606,7 +606,7 @@ alloc_ok:
ret = drm_addmap(dev, block->start, block->size,
_DRM_SCATTER_GATHER, 0, &block->map);
- if (ret) {
+ if (ret) {
nouveau_mem_free_block(block);
return NULL;
}
@@ -676,5 +676,3 @@ int nouveau_ioctl_mem_free(struct drm_device *dev, void *data, struct drm_file *
nouveau_mem_free(dev, block);
return 0;
}
-
-
diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c
index 31e2b244..82c8ab7d 100644
--- a/shared-core/nouveau_notifier.c
+++ b/shared-core/nouveau_notifier.c
@@ -115,7 +115,7 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle,
} else {
target = NV_DMA_TARGET_AGP;
}
- } else
+ } else
if (chan->notifier_block->flags & NOUVEAU_MEM_PCI) {
target = NV_DMA_TARGET_PCI_NONLINEAR;
} else {
@@ -163,4 +163,3 @@ nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data,
return 0;
}
-
diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c
index fbce7702..b6bf759d 100644
--- a/shared-core/nouveau_object.c
+++ b/shared-core/nouveau_object.c
@@ -524,7 +524,7 @@ nouveau_gpuobj_ref_find(struct nouveau_channel *chan, uint32_t handle,
struct nouveau_gpuobj_ref *ref;
struct list_head *entry, *tmp;
- list_for_each_safe(entry, tmp, &chan->ramht_refs) {
+ list_for_each_safe(entry, tmp, &chan->ramht_refs) {
ref = list_entry(entry, struct nouveau_gpuobj_ref, list);
if (ref->handle == handle) {
@@ -616,7 +616,7 @@ nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class)
DMA objects are used to reference a piece of memory in the
framebuffer, PCI or AGP address space. Each object is 16 bytes big
and looks as follows:
-
+
entry[0]
11:0 class (seems like I can always use 0 here)
12 page table present?
@@ -648,7 +648,7 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
struct drm_nouveau_private *dev_priv = dev->dev_private;
int ret;
uint32_t is_scatter_gather = 0;
-
+
/* Total number of pages covered by the request.
*/
const unsigned int page_count = (size + PAGE_SIZE - 1) / PAGE_SIZE;
@@ -671,7 +671,7 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
default:
break;
}
-
+
ret = nouveau_gpuobj_new(dev, chan,
is_scatter_gather ? ((page_count << 2) + 12) : nouveau_gpuobj_class_instmem_size(dev, class),
16,
@@ -687,11 +687,11 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
adjust = offset & 0x00000fff;
if (access != NV_DMA_ACCESS_RO)
pte_flags |= (1<<1);
-
- if ( ! is_scatter_gather )
+
+ if ( ! is_scatter_gather )
{
frame = offset & ~0x00000fff;
-
+
INSTANCE_WR(*gpuobj, 0, ((1<<12) | (1<<13) |
(adjust << 20) |
(access << 14) |
@@ -701,7 +701,7 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
INSTANCE_WR(*gpuobj, 2, frame | pte_flags);
INSTANCE_WR(*gpuobj, 3, frame | pte_flags);
}
- else
+ else
{
/* Intial page entry in the scatter-gather area that
* corresponds to the base offset
@@ -728,7 +728,7 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
/*write starting at the third dword*/
instance_offset = 2;
-
+
/*for each PAGE, get its bus address, fill in the page table entry, and advance*/
for (i = 0; i < page_count; i++) {
if (dev->sg->busaddr[idx] == 0) {
@@ -745,12 +745,12 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
}
frame = (uint32_t) dev->sg->busaddr[idx];
- INSTANCE_WR(*gpuobj, instance_offset,
+ INSTANCE_WR(*gpuobj, instance_offset,
frame | pte_flags);
-
+
idx++;
instance_offset ++;
- }
+ }
}
} else {
uint32_t flags0, flags5;
@@ -848,7 +848,7 @@ nouveau_gpuobj_gart_dma_new(struct nouveau_channel *chan,
entry[0]:
11:0 class (maybe uses more bits here?)
17 user clip enable
- 21:19 patch config
+ 21:19 patch config
25 patch status valid ?
entry[1]:
15:0 DMA notifier (maybe 20:0)
@@ -986,7 +986,7 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
/* NV50 VM, point offset 0-512MiB at shared PCIEGART table */
if (dev_priv->card_type >= NV_50) {
uint32_t vm_offset;
-
+
vm_offset = (dev_priv->chipset & 0xf0) == 0x50 ? 0x1400 : 0x200;
vm_offset += chan->ramin->gpuobj->im_pramin->start;
if ((ret = nouveau_gpuobj_new_fake(dev, vm_offset, ~0, 0x4000,
@@ -1074,7 +1074,7 @@ nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
DRM_DEBUG("ch%d\n", chan->id);
- list_for_each_safe(entry, tmp, &chan->ramht_refs) {
+ list_for_each_safe(entry, tmp, &chan->ramht_refs) {
ref = list_entry(entry, struct nouveau_gpuobj_ref, list);
nouveau_gpuobj_ref_del(dev, &ref);
@@ -1104,7 +1104,7 @@ int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(init->channel, file_priv, chan);
//FIXME: check args, only allow trusted objects to be created
-
+
if (init->handle == ~0)
return -EINVAL;
@@ -1145,4 +1145,3 @@ int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
return 0;
}
-
diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h
index 4dc3b7fa..43573f2c 100644
--- a/shared-core/nouveau_reg.h
+++ b/shared-core/nouveau_reg.h
@@ -550,4 +550,3 @@
#define NV40_RAMFC_UNK_48 0x48
#define NV40_RAMFC_UNK_4C 0x4C
#define NV40_RAMFC_UNK_50 0x50
-
diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c
index fee17d0a..610d24e2 100644
--- a/shared-core/nouveau_state.c
+++ b/shared-core/nouveau_state.c
@@ -1,4 +1,4 @@
-/*
+/*
* Copyright 2005 Stephane Marchesin
* All Rights Reserved.
*
@@ -40,7 +40,7 @@ static int nouveau_init_card_mappings(struct drm_device *dev)
/* map the mmio regs */
ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
- drm_get_resource_len(dev, 0),
+ drm_get_resource_len(dev, 0),
_DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
if (ret) {
DRM_ERROR("Unable to initialize the mmio mapping (%d). "
@@ -431,7 +431,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
DRM_DEBUG("vendor: 0x%X device: 0x%X class: 0x%X\n", dev->pci_vendor, dev->pci_device, dev->pdev->class);
/* Time to determine the card architecture */
- regs = ioremap_nocache(pci_resource_start(dev->pdev, 0), 0x8);
+ regs = ioremap_nocache(pci_resource_start(dev->pdev, 0), 0x8);
if (!regs) {
DRM_ERROR("Could not ioremap to determine register\n");
return -ENOMEM;
@@ -559,7 +559,7 @@ int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *
case NOUVEAU_GETPARAM_PCI_PHYSICAL:
if ( dev -> sg )
getparam->value=(uint64_t) dev->sg->virtual;
- else
+ else
{
DRM_ERROR("Requested PCIGART address, while no PCIGART was created\n");
return -EINVAL;
@@ -641,5 +641,3 @@ void nouveau_wait_for_idle(struct drm_device *dev)
}
}
}
-
-
diff --git a/shared-core/nouveau_swmthd.c b/shared-core/nouveau_swmthd.c
index 66ef6233..c3666bfd 100644
--- a/shared-core/nouveau_swmthd.c
+++ b/shared-core/nouveau_swmthd.c
@@ -189,5 +189,3 @@ static void nouveau_NV04_setcontext_sw_method(struct drm_device *dev, uint32_t o
return 1;
}
-
-
diff --git a/shared-core/nouveau_swmthd.h b/shared-core/nouveau_swmthd.h
index df8c7400..5b9409fb 100644
--- a/shared-core/nouveau_swmthd.h
+++ b/shared-core/nouveau_swmthd.h
@@ -31,4 +31,3 @@
*/
int nouveau_sw_method_execute(struct drm_device *dev, uint32_t oclass, uint32_t method); /* execute the given software method, returns 0 on success */
-
diff --git a/shared-core/nv04_fb.c b/shared-core/nv04_fb.c
index 534fb50b..58a92470 100644
--- a/shared-core/nv04_fb.c
+++ b/shared-core/nv04_fb.c
@@ -21,4 +21,3 @@ void
nv04_fb_takedown(struct drm_device *dev)
{
}
-
diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c
index d750ced8..d172302c 100644
--- a/shared-core/nv04_fifo.c
+++ b/shared-core/nv04_fifo.c
@@ -71,7 +71,7 @@ nv04_fifo_destroy_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
-
+
NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
nouveau_gpuobj_ref_del(dev, &chan->ramfc);
@@ -88,11 +88,11 @@ nv04_fifo_load_context(struct nouveau_channel *chan)
NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET));
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT));
-
+
tmp = RAMFC_RD(DMA_INSTANCE);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
-
+
NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, RAMFC_RD(DMA_STATE));
NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, RAMFC_RD(DMA_FETCH));
NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, RAMFC_RD(ENGINE));
@@ -123,7 +123,6 @@ nv04_fifo_save_context(struct nouveau_channel *chan)
RAMFC_WR(DMA_FETCH, NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE));
RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1));
-
+
return 0;
}
-
diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c
index cffa3e4a..04dbf0ed 100644
--- a/shared-core/nv04_graph.c
+++ b/shared-core/nv04_graph.c
@@ -1,4 +1,4 @@
-/*
+/*
* Copyright 2007 Stephane Marchesin
* All Rights Reserved.
*
diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c
index 5a446450..56968181 100644
--- a/shared-core/nv04_instmem.c
+++ b/shared-core/nv04_instmem.c
@@ -134,7 +134,7 @@ nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
if (gpuobj->im_bound)
dev_priv->Engine.instmem.unbind(dev, gpuobj);
gpuobj->im_backing = NULL;
- }
+ }
}
int
@@ -156,4 +156,3 @@ nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
gpuobj->im_bound = 0;
return 0;
}
-
diff --git a/shared-core/nv04_mc.c b/shared-core/nv04_mc.c
index eee0c50c..24c1f7b3 100644
--- a/shared-core/nv04_mc.c
+++ b/shared-core/nv04_mc.c
@@ -20,4 +20,3 @@ void
nv04_mc_takedown(struct drm_device *dev)
{
}
-
diff --git a/shared-core/nv04_timer.c b/shared-core/nv04_timer.c
index 08a27f4f..88dff36d 100644
--- a/shared-core/nv04_timer.c
+++ b/shared-core/nv04_timer.c
@@ -42,4 +42,3 @@ void
nv04_timer_takedown(struct drm_device *dev)
{
}
-
diff --git a/shared-core/nv10_fb.c b/shared-core/nv10_fb.c
index 7fff5b3f..6e0773ac 100644
--- a/shared-core/nv10_fb.c
+++ b/shared-core/nv10_fb.c
@@ -23,4 +23,3 @@ void
nv10_fb_takedown(struct drm_device *dev)
{
}
-
diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c
index c86725d2..45d2603a 100644
--- a/shared-core/nv10_fifo.c
+++ b/shared-core/nv10_fifo.c
@@ -157,4 +157,3 @@ nv10_fifo_save_context(struct nouveau_channel *chan)
return 0;
}
-
diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c
index c6319b8f..606fb43f 100644
--- a/shared-core/nv10_graph.c
+++ b/shared-core/nv10_graph.c
@@ -1,4 +1,4 @@
-/*
+/*
* Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
* All Rights Reserved.
*
@@ -732,7 +732,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
if (last) {
nouveau_wait_for_idle(dev);
nv10_graph_save_context(last);
- }
+ }
nouveau_wait_for_idle(dev);
@@ -907,4 +907,3 @@ int nv10_graph_init(struct drm_device *dev) {
void nv10_graph_takedown(struct drm_device *dev)
{
}
-
diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c
index 3d9549a4..a21fde71 100644
--- a/shared-core/nv20_graph.c
+++ b/shared-core/nv20_graph.c
@@ -887,4 +887,3 @@ int nv30_graph_init(struct drm_device *dev)
return 0;
}
-
diff --git a/shared-core/nv40_fb.c b/shared-core/nv40_fb.c
index 2cbb40e4..ceae8079 100644
--- a/shared-core/nv40_fb.c
+++ b/shared-core/nv40_fb.c
@@ -53,4 +53,3 @@ void
nv40_fb_takedown(struct drm_device *dev)
{
}
-
diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c
index ce3f8fdd..5b3eda09 100644
--- a/shared-core/nv40_fifo.c
+++ b/shared-core/nv40_fifo.c
@@ -205,4 +205,3 @@ nv40_fifo_init(struct drm_device *dev)
NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
return 0;
}
-
diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c
index 7ce4273d..fdf51519 100644
--- a/shared-core/nv40_graph.c
+++ b/shared-core/nv40_graph.c
@@ -304,7 +304,7 @@ nv43_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int i;
-
+
INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start);
INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);
INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);
@@ -1555,7 +1555,7 @@ nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
NV_WRITE(NV40_PGRAPH_CTXCTL_0310, tmp);
-
+
tmp = NV_READ(NV40_PGRAPH_CTXCTL_0304);
tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
NV_WRITE(NV40_PGRAPH_CTXCTL_0304, tmp);
@@ -1877,35 +1877,35 @@ static uint32_t nv49_4b_ctx_voodoo[] ={
static uint32_t nv4a_ctx_voodoo[] = {
- 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
- 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409965, 0x00409e06,
- 0x0040ac68, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
- 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061,
- 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,
- 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,
- 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,
- 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,
- 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,
- 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407de6, 0x002000f1,
- 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b,
- 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6,
- 0x001646cc, 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700,
- 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003,
- 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200232, 0x0060000a,
- 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940,
- 0x00140965, 0x00148a00, 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00,
- 0x0010cd04, 0x0010cd08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00,
- 0x00104f06, 0x002002c8, 0x0060000a, 0x00300000, 0x00200080, 0x00407300,
- 0x00200084, 0x00800001, 0x00200510, 0x0060000a, 0x002037e0, 0x0040798a,
- 0x00201320, 0x00800029, 0x00407d84, 0x00201560, 0x00800002, 0x00409100,
- 0x00600006, 0x00700003, 0x00408ae6, 0x00700080, 0x0020007a, 0x0060000a,
- 0x00104280, 0x002002c8, 0x0060000a, 0x00200004, 0x00800001, 0x00700000,
- 0x00200000, 0x0060000a, 0x00106002, 0x0040ac84, 0x00700002, 0x00600004,
- 0x0040ac68, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x00700080,
- 0x00400a84, 0x00700002, 0x00400a68, 0x00500060, 0x00600007, 0x00409d88,
- 0x0060000f, 0x00000000, 0x00500060, 0x00200000, 0x0060000a, 0x00700000,
- 0x00106001, 0x00700083, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020,
- 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68, 0x0040ae06, 0x0040af05,
+ 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
+ 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409965, 0x00409e06,
+ 0x0040ac68, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
+ 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061,
+ 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,
+ 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,
+ 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,
+ 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,
+ 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,
+ 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407de6, 0x002000f1,
+ 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b,
+ 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6,
+ 0x001646cc, 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700,
+ 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003,
+ 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200232, 0x0060000a,
+ 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940,
+ 0x00140965, 0x00148a00, 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00,
+ 0x0010cd04, 0x0010cd08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00,
+ 0x00104f06, 0x002002c8, 0x0060000a, 0x00300000, 0x00200080, 0x00407300,
+ 0x00200084, 0x00800001, 0x00200510, 0x0060000a, 0x002037e0, 0x0040798a,
+ 0x00201320, 0x00800029, 0x00407d84, 0x00201560, 0x00800002, 0x00409100,
+ 0x00600006, 0x00700003, 0x00408ae6, 0x00700080, 0x0020007a, 0x0060000a,
+ 0x00104280, 0x002002c8, 0x0060000a, 0x00200004, 0x00800001, 0x00700000,
+ 0x00200000, 0x0060000a, 0x00106002, 0x0040ac84, 0x00700002, 0x00600004,
+ 0x0040ac68, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x00700080,
+ 0x00400a84, 0x00700002, 0x00400a68, 0x00500060, 0x00600007, 0x00409d88,
+ 0x0060000f, 0x00000000, 0x00500060, 0x00200000, 0x0060000a, 0x00700000,
+ 0x00106001, 0x00700083, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020,
+ 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68, 0x0040ae06, 0x0040af05,
0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
};
@@ -2026,7 +2026,7 @@ nv40_graph_init(struct drm_device *dev)
NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, ctx_voodoo[i]);
i++;
}
- }
+ }
/* No context present currently */
NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
@@ -2221,4 +2221,3 @@ nv40_graph_init(struct drm_device *dev)
void nv40_graph_takedown(struct drm_device *dev)
{
}
-
diff --git a/shared-core/nv40_mc.c b/shared-core/nv40_mc.c
index c7db9023..ead6f87f 100644
--- a/shared-core/nv40_mc.c
+++ b/shared-core/nv40_mc.c
@@ -36,4 +36,3 @@ void
nv40_mc_takedown(struct drm_device *dev)
{
}
-
diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c
index 7859544a..f77de6e7 100644
--- a/shared-core/nv50_fifo.c
+++ b/shared-core/nv50_fifo.c
@@ -324,4 +324,3 @@ nv50_fifo_save_context(struct nouveau_channel *chan)
DRM_ERROR("stub!\n");
return 0;
}
-
diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c
index e5bbf65e..5814abd4 100644
--- a/shared-core/nv50_graph.c
+++ b/shared-core/nv50_graph.c
@@ -177,7 +177,7 @@ nv50_graph_init_ctxctl(struct drm_device *dev)
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
}
-int
+int
nv50_graph_init(struct drm_device *dev)
{
DRM_DEBUG("\n");
@@ -262,7 +262,7 @@ nv50_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst | (1<<31));
NV_WRITE(0x400824, NV_READ(0x400824) |
(save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
- NV40_PGRAPH_CTXCTL_0310_XFER_LOAD));
+ NV40_PGRAPH_CTXCTL_0310_XFER_LOAD));
NV_WRITE(NV40_PGRAPH_CTXCTL_0304, NV40_PGRAPH_CTXCTL_0304_XFER_CTX);
for (i = 0; i < tv; i++) {
@@ -313,4 +313,3 @@ nv50_graph_save_context(struct nouveau_channel *chan)
return nv50_graph_transfer_context(dev, inst, 1);
}
-
diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c
index 1eeb54df..c80574a9 100644
--- a/shared-core/nv50_instmem.c
+++ b/shared-core/nv50_instmem.c
@@ -69,7 +69,7 @@ nv50_instmem_init(struct drm_device *dev)
return -ENOMEM;
dev_priv->Engine.instmem.priv = priv;
- /* Reserve the last MiB of VRAM, we should probably try to avoid
+ /* Reserve the last MiB of VRAM, we should probably try to avoid
* setting up the below tables over the top of the VBIOS image at
* some point.
*/
@@ -144,7 +144,7 @@ nv50_instmem_init(struct drm_device *dev)
BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1);
else
BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009);
- BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
+ BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
}
BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
@@ -259,7 +259,7 @@ nv50_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
dev_priv->Engine.instmem.unbind(dev, gpuobj);
nouveau_mem_free(dev, gpuobj->im_backing);
gpuobj->im_backing = NULL;
- }
+ }
}
int
@@ -317,4 +317,3 @@ nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
gpuobj->im_bound = 0;
return 0;
}
-
diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c
index 5bed45bc..8ce128bd 100644
--- a/shared-core/r128_cce.c
+++ b/shared-core/r128_cce.c
@@ -324,7 +324,7 @@ static void r128_cce_init_ring_buffer(struct drm_device * dev,
ring_start = dev_priv->cce_ring->offset - dev->agp->base;
else
#endif
- ring_start = dev_priv->cce_ring->offset -
+ ring_start = dev_priv->cce_ring->offset -
(unsigned long)dev->sg->virtual;
R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h
index abb99898..4d27f549 100644
--- a/shared-core/r128_drv.h
+++ b/shared-core/r128_drv.h
@@ -493,7 +493,7 @@ do { \
write * sizeof(u32) ); \
} \
if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \
- DRM_ERROR( \
+ DRM_ERROR( \
"ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
((dev_priv->ring.tail + _nr) & tail_mask), \
write, __LINE__); \
diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c
index fe46c2d2..6ab907c6 100644
--- a/shared-core/r300_cmdbuf.c
+++ b/shared-core/r300_cmdbuf.c
@@ -486,7 +486,7 @@ static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
if (cmd[0] & 0x8000) {
u32 offset;
- if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
+ if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
| RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
offset = cmd[2] << 10;
ret = !radeon_check_offset(dev_priv, offset);
@@ -504,7 +504,7 @@ static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
DRM_ERROR("Invalid bitblt second offset is %08X\n", offset);
return -EINVAL;
}
-
+
}
}
@@ -723,53 +723,53 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
u32 *ref_age_base;
u32 i, buf_idx, h_pending;
RING_LOCALS;
-
+
if (cmdbuf->bufsz < sizeof(uint64_t) + header.scratch.n_bufs * sizeof(buf_idx) ) {
return -EINVAL;
}
-
+
if (header.scratch.reg >= 5) {
return -EINVAL;
}
-
+
dev_priv->scratch_ages[header.scratch.reg] ++;
-
+
ref_age_base = (u32 *)(unsigned long)*((uint64_t *)cmdbuf->buf);
-
+
cmdbuf->buf += sizeof(uint64_t);
cmdbuf->bufsz -= sizeof(uint64_t);
-
+
for (i=0; i < header.scratch.n_bufs; i++) {
buf_idx = *(u32 *)cmdbuf->buf;
buf_idx *= 2; /* 8 bytes per buf */
-
+
if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) {
return -EINVAL;
}
-
+
if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) {
return -EINVAL;
}
-
+
if (h_pending == 0) {
return -EINVAL;
}
-
+
h_pending--;
-
+
if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) {
return -EINVAL;
}
-
+
cmdbuf->buf += sizeof(buf_idx);
cmdbuf->bufsz -= sizeof(buf_idx);
}
-
+
BEGIN_RING(2);
OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) );
OUT_RING( dev_priv->scratch_ages[header.scratch.reg] );
ADVANCE_RING();
-
+
return 0;
}
@@ -918,7 +918,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
goto cleanup;
}
break;
-
+
default:
DRM_ERROR("bad cmd_type %i at %p\n",
header.header.cmd_type,
diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h
index e59919be..29198c8a 100644
--- a/shared-core/r300_reg.h
+++ b/shared-core/r300_reg.h
@@ -856,13 +856,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_TX_FORMAT_W8Z8Y8X8 0xC
# define R300_TX_FORMAT_W2Z10Y10X10 0xD
# define R300_TX_FORMAT_W16Z16Y16X16 0xE
-# define R300_TX_FORMAT_DXT1 0xF
-# define R300_TX_FORMAT_DXT3 0x10
-# define R300_TX_FORMAT_DXT5 0x11
+# define R300_TX_FORMAT_DXT1 0xF
+# define R300_TX_FORMAT_DXT3 0x10
+# define R300_TX_FORMAT_DXT5 0x11
# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
-# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
-# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
-# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
+# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
+# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
+# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
/* 0x16 - some 16 bit green format.. ?? */
# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */
# define R300_TX_FORMAT_CUBIC_MAP (1 << 26)
@@ -870,19 +870,19 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* gap */
/* Floating point formats */
/* Note - hardware supports both 16 and 32 bit floating point */
-# define R300_TX_FORMAT_FL_I16 0x18
-# define R300_TX_FORMAT_FL_I16A16 0x19
+# define R300_TX_FORMAT_FL_I16 0x18
+# define R300_TX_FORMAT_FL_I16A16 0x19
# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
-# define R300_TX_FORMAT_FL_I32 0x1B
-# define R300_TX_FORMAT_FL_I32A32 0x1C
+# define R300_TX_FORMAT_FL_I32 0x1B
+# define R300_TX_FORMAT_FL_I32A32 0x1C
# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
/* alpha modes, convenience mostly */
/* if you have alpha, pick constant appropriate to the
number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
-# define R300_TX_FORMAT_ALPHA_1CH 0x000
-# define R300_TX_FORMAT_ALPHA_2CH 0x200
-# define R300_TX_FORMAT_ALPHA_4CH 0x600
-# define R300_TX_FORMAT_ALPHA_NONE 0xA00
+# define R300_TX_FORMAT_ALPHA_1CH 0x000
+# define R300_TX_FORMAT_ALPHA_2CH 0x200
+# define R300_TX_FORMAT_ALPHA_4CH 0x600
+# define R300_TX_FORMAT_ALPHA_NONE 0xA00
/* Swizzling */
/* constants */
# define R300_TX_FORMAT_X 0
@@ -1363,11 +1363,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_RB3D_Z_DISABLED_2 0x00000014
# define R300_RB3D_Z_TEST 0x00000012
# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
-# define R300_RB3D_Z_WRITE_ONLY 0x00000006
+# define R300_RB3D_Z_WRITE_ONLY 0x00000006
# define R300_RB3D_Z_TEST 0x00000012
# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
-# define R300_RB3D_Z_WRITE_ONLY 0x00000006
+# define R300_RB3D_Z_WRITE_ONLY 0x00000006
# define R300_RB3D_STENCIL_ENABLE 0x00000001
#define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index c4e13bb2..958a179f 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -695,7 +695,7 @@ static const u32 R300_cp_microcode[][2] = {
{ 0x0000e571, 0x00000004 },
{ 0x0000e572, 0x0000000c },
{ 0x0000a000, 0x00000004 },
- { 0x0140a000, 0x00000004 },
+ { 0x0140a000, 0x00000004 },
{ 0x0000e568, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00000089, 0x00000018 },
@@ -1127,7 +1127,7 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
{
u32 ring_start, cur_read_ptr;
u32 tmp;
-
+
/* Initialize the memory controller. With new memory map, the fb location
* is not changed, it should have been properly initialized already. Part
* of the problem is that the code below is bogus, assuming the GART is
@@ -1364,7 +1364,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
return;
}
- tmp = RADEON_READ(RADEON_AIC_CNTL);
+ tmp = RADEON_READ(RADEON_AIC_CNTL);
if (on) {
RADEON_WRITE(RADEON_AIC_CNTL,
@@ -1592,7 +1592,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
& 0xffff) << 16;
- dev_priv->fb_size =
+ dev_priv->fb_size =
((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
- dev_priv->fb_location;
@@ -1639,7 +1639,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
((base + dev_priv->gart_size) & 0xfffffffful) < base)
base = dev_priv->fb_location
- dev_priv->gart_size;
- }
+ }
dev_priv->gart_vm_start = base & 0xffc00000u;
if (dev_priv->gart_vm_start != base)
DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h
index b0ef702b..4594a837 100644
--- a/shared-core/radeon_drm.h
+++ b/shared-core/radeon_drm.h
@@ -223,10 +223,10 @@ typedef union {
#define R300_CMD_CP_DELAY 5
#define R300_CMD_DMA_DISCARD 6
#define R300_CMD_WAIT 7
-# define R300_WAIT_2D 0x1
-# define R300_WAIT_3D 0x2
-# define R300_WAIT_2D_CLEAN 0x3
-# define R300_WAIT_3D_CLEAN 0x4
+# define R300_WAIT_2D 0x1
+# define R300_WAIT_3D 0x2
+# define R300_WAIT_2D_CLEAN 0x3
+# define R300_WAIT_3D_CLEAN 0x4
#define R300_CMD_SCRATCH 8
typedef union {
@@ -723,7 +723,7 @@ typedef struct drm_radeon_surface_free {
unsigned int address;
} drm_radeon_surface_free_t;
-#define DRM_RADEON_VBLANK_CRTC1 1
-#define DRM_RADEON_VBLANK_CRTC2 2
+#define DRM_RADEON_VBLANK_CRTC1 1
+#define DRM_RADEON_VBLANK_CRTC2 2
#endif
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index e7264a88..a1745cdd 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -436,7 +436,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_PCIE_INDEX 0x0030
#define RADEON_PCIE_DATA 0x0034
#define RADEON_PCIE_TX_GART_CNTL 0x10
-# define RADEON_PCIE_TX_GART_EN (1 << 0)
+# define RADEON_PCIE_TX_GART_EN (1 << 0)
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
@@ -446,7 +446,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
-#define RADEON_PCIE_TX_GART_BASE 0x13
+#define RADEON_PCIE_TX_GART_BASE 0x13
#define RADEON_PCIE_TX_GART_START_LO 0x14
#define RADEON_PCIE_TX_GART_START_HI 0x15
#define RADEON_PCIE_TX_GART_END_LO 0x16
@@ -520,12 +520,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_GEN_INT_STATUS 0x0044
# define RADEON_CRTC_VBLANK_STAT (1 << 0)
-# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
+# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
-# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
+# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
# define RADEON_SW_INT_TEST (1 << 25)
-# define RADEON_SW_INT_TEST_ACK (1 << 25)
+# define RADEON_SW_INT_TEST_ACK (1 << 25)
# define RADEON_SW_INT_FIRE (1 << 26)
#define RADEON_HOST_PATH_CNTL 0x0130
@@ -644,30 +644,30 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
*/
#define RADEON_RBBM_STATUS 0x0e40
/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
-/* #define RADEON_RBBM_STATUS 0x1740 */
+/* #define RADEON_RBBM_STATUS 0x1740 */
/* bits 6:0 are dword slots available in the cmd fifo */
# define RADEON_RBBM_FIFOCNT_MASK 0x007f
-# define RADEON_HIRQ_ON_RBB (1 << 8)
-# define RADEON_CPRQ_ON_RBB (1 << 9)
-# define RADEON_CFRQ_ON_RBB (1 << 10)
-# define RADEON_HIRQ_IN_RTBUF (1 << 11)
-# define RADEON_CPRQ_IN_RTBUF (1 << 12)
-# define RADEON_CFRQ_IN_RTBUF (1 << 13)
-# define RADEON_PIPE_BUSY (1 << 14)
-# define RADEON_ENG_EV_BUSY (1 << 15)
-# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
-# define RADEON_E2_BUSY (1 << 17)
-# define RADEON_RB2D_BUSY (1 << 18)
-# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
-# define RADEON_VAP_BUSY (1 << 20)
-# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
-# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
-# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
-# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
-# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
-# define RADEON_GA_BUSY (1 << 26)
-# define RADEON_CBA2D_BUSY (1 << 27)
-# define RADEON_RBBM_ACTIVE (1 << 31)
+# define RADEON_HIRQ_ON_RBB (1 << 8)
+# define RADEON_CPRQ_ON_RBB (1 << 9)
+# define RADEON_CFRQ_ON_RBB (1 << 10)
+# define RADEON_HIRQ_IN_RTBUF (1 << 11)
+# define RADEON_CPRQ_IN_RTBUF (1 << 12)
+# define RADEON_CFRQ_IN_RTBUF (1 << 13)
+# define RADEON_PIPE_BUSY (1 << 14)
+# define RADEON_ENG_EV_BUSY (1 << 15)
+# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
+# define RADEON_E2_BUSY (1 << 17)
+# define RADEON_RB2D_BUSY (1 << 18)
+# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
+# define RADEON_VAP_BUSY (1 << 20)
+# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
+# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
+# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
+# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
+# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
+# define RADEON_GA_BUSY (1 << 26)
+# define RADEON_CBA2D_BUSY (1 << 27)
+# define RADEON_RBBM_ACTIVE (1 << 31)
#define RADEON_RE_LINE_PATTERN 0x1cd0
#define RADEON_RE_MISC 0x26c4
#define RADEON_RE_TOP_LEFT 0x26c0
@@ -1213,7 +1213,7 @@ do { \
write, dev_priv->ring.tail ); \
} \
if (((dev_priv->ring.tail + _nr) & mask) != write) { \
- DRM_ERROR( \
+ DRM_ERROR( \
"ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
((dev_priv->ring.tail + _nr) & mask), \
write, __LINE__); \
diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index e3aadfb9..71b19b1b 100644
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -3069,7 +3069,7 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
return -EINVAL;
value = RADEON_SCRATCH_REG_OFFSET;
break;
-
+
case RADEON_PARAM_CARD_TYPE:
if (dev_priv->flags & RADEON_IS_PCIE)
value = RADEON_CARD_PCIE;
diff --git a/shared-core/savage_bci.c b/shared-core/savage_bci.c
index 32ac5ac2..7710ba0d 100644
--- a/shared-core/savage_bci.c
+++ b/shared-core/savage_bci.c
@@ -584,7 +584,7 @@ int savage_driver_firstopen(struct drm_device *dev)
* MTRRs. */
dev_priv->mtrr[0].base = fb_base;
dev_priv->mtrr[0].size = 0x01000000;
- dev_priv->mtrr[0].handle =
+ dev_priv->mtrr[0].handle =
drm_mtrr_add(dev_priv->mtrr[0].base,
dev_priv->mtrr[0].size, DRM_MTRR_WC);
dev_priv->mtrr[1].base = fb_base+0x02000000;
@@ -595,7 +595,7 @@ int savage_driver_firstopen(struct drm_device *dev)
dev_priv->mtrr[2].base = fb_base+0x04000000;
dev_priv->mtrr[2].size = 0x04000000;
dev_priv->mtrr[2].handle =
- drm_mtrr_add(dev_priv->mtrr[2].base,
+ drm_mtrr_add(dev_priv->mtrr[2].base,
dev_priv->mtrr[2].size, DRM_MTRR_WC);
} else {
DRM_ERROR("strange pci_resource_len %08lx\n",
@@ -615,7 +615,7 @@ int savage_driver_firstopen(struct drm_device *dev)
* aperture. */
dev_priv->mtrr[0].base = fb_base;
dev_priv->mtrr[0].size = 0x08000000;
- dev_priv->mtrr[0].handle =
+ dev_priv->mtrr[0].handle =
drm_mtrr_add(dev_priv->mtrr[0].base,
dev_priv->mtrr[0].size, DRM_MTRR_WC);
} else {
@@ -834,7 +834,7 @@ static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init)
}
front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8);
back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
- depth_stride =
+ depth_stride =
dev_priv->depth_pitch / (dev_priv->depth_bpp / 8);
dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE |
@@ -1092,4 +1092,3 @@ struct drm_ioctl_desc savage_ioctls[] = {
};
int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls);
-
diff --git a/shared-core/savage_drv.h b/shared-core/savage_drv.h
index d86bac04..b9124b1a 100644
--- a/shared-core/savage_drv.h
+++ b/shared-core/savage_drv.h
@@ -237,7 +237,7 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
*/
#define SAVAGE_STATUS_WORD0 0x48C00
#define SAVAGE_STATUS_WORD1 0x48C04
-#define SAVAGE_ALT_STATUS_WORD0 0x48C60
+#define SAVAGE_ALT_STATUS_WORD0 0x48C60
#define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff
#define SAVAGE_FIFO_USED_MASK_S4 0x001fffff
@@ -310,7 +310,7 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
#define SAVAGE_DESTCTRL_S3D 0x34
#define SAVAGE_SCSTART_S3D 0x35
#define SAVAGE_SCEND_S3D 0x36
-#define SAVAGE_ZWATERMARK_S3D 0x37
+#define SAVAGE_ZWATERMARK_S3D 0x37
#define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38
/* common stuff */
#define SAVAGE_VERTBUFADDR 0x3e
diff --git a/shared-core/savage_state.c b/shared-core/savage_state.c
index dd593340..61ec11cc 100644
--- a/shared-core/savage_state.c
+++ b/shared-core/savage_state.c
@@ -32,7 +32,7 @@ void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv,
uint32_t scstart = dev_priv->state.s3d.new_scstart;
uint32_t scend = dev_priv->state.s3d.new_scend;
scstart = (scstart & ~SAVAGE_SCISSOR_MASK_S3D) |
- ((uint32_t)pbox->x1 & 0x000007ff) |
+ ((uint32_t)pbox->x1 & 0x000007ff) |
(((uint32_t)pbox->y1 << 16) & 0x07ff0000);
scend = (scend & ~SAVAGE_SCISSOR_MASK_S3D) |
(((uint32_t)pbox->x2-1) & 0x000007ff) |
@@ -966,7 +966,7 @@ int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_
int ret = 0;
DRM_DEBUG("\n");
-
+
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (dma && dma->buflist) {
diff --git a/shared-core/via_dma.c b/shared-core/via_dma.c
index bd737a7e..89753aa6 100644
--- a/shared-core/via_dma.c
+++ b/shared-core/via_dma.c
@@ -1,11 +1,11 @@
/* via_dma.c -- DMA support for the VIA Unichrome/Pro
- *
+ *
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
* All Rights Reserved.
- *
+ *
* Copyright 2004 The Unichrome project.
* All Rights Reserved.
*
@@ -23,14 +23,14 @@
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Authors:
- * Tungsten Graphics,
- * Erdi Chen,
+ * Authors:
+ * Tungsten Graphics,
+ * Erdi Chen,
* Thomas Hellstrom.
*/
@@ -47,12 +47,12 @@
dev_priv->dma_low +=8; \
}
-#define via_flush_write_combine() DRM_MEMORYBARRIER()
+#define via_flush_write_combine() DRM_MEMORYBARRIER()
#define VIA_OUT_RING_QW(w1,w2) \
*vb++ = (w1); \
*vb++ = (w2); \
- dev_priv->dma_low += 8;
+ dev_priv->dma_low += 8;
static void via_cmdbuf_start(drm_via_private_t * dev_priv);
static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
@@ -70,9 +70,9 @@ static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv)
{
uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
-
- return ((hw_addr <= dev_priv->dma_low) ?
- (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
+
+ return ((hw_addr <= dev_priv->dma_low) ?
+ (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
(hw_addr - dev_priv->dma_low));
}
@@ -173,7 +173,7 @@ static int via_initialize(struct drm_device * dev,
}
if (!dev->agp || !dev->agp->base) {
- DRM_ERROR("%s called with no agp memory available\n",
+ DRM_ERROR("%s called with no agp memory available\n",
__FUNCTION__);
return -EFAULT;
}
@@ -476,12 +476,12 @@ static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
vb = via_get_dma(dev_priv);
VIA_OUT_RING_QW( HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
- (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
+ (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
- cmd_addr = (addr) ? addr :
+ cmd_addr = (addr) ? addr :
agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
(cmd_addr & HC_HAGPBpL_MASK));
@@ -514,8 +514,8 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv)
command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
((end_addr & 0xff000000) >> 16));
- dev_priv->last_pause_ptr =
- via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
+ dev_priv->last_pause_ptr =
+ via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
&pause_addr_hi, & pause_addr_lo, 1) - 1;
via_flush_write_combine();
@@ -579,7 +579,7 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
&jump_addr_lo, 0);
-
+
dev_priv->dma_wrap = dev_priv->dma_low;
@@ -606,7 +606,7 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
{
- via_cmdbuf_jump(dev_priv);
+ via_cmdbuf_jump(dev_priv);
}
static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
@@ -687,12 +687,12 @@ static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *
}
#ifndef VIA_HAVE_DMABLIT
-int
+int
via_dma_blit_sync( struct drm_device *dev, void *data, struct drm_file *file_priv ) {
DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");
return -EINVAL;
}
-int
+int
via_dma_blit( struct drm_device *dev, void *data, struct drm_file *file_priv ) {
DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");
return -EINVAL;
diff --git a/shared-core/via_drm.h b/shared-core/via_drm.h
index b15785b3..7ee69d28 100644
--- a/shared-core/via_drm.h
+++ b/shared-core/via_drm.h
@@ -49,7 +49,7 @@
#define VIA_DRM_DRIVER_PATCHLEVEL 1
#define VIA_DRM_DRIVER_VERSION (((VIA_DRM_DRIVER_MAJOR) << 16) | (VIA_DRM_DRIVER_MINOR))
-#define VIA_NR_SAREA_CLIPRECTS 8
+#define VIA_NR_SAREA_CLIPRECTS 8
#define VIA_NR_XVMC_PORTS 10
#define VIA_NR_XVMC_LOCKS 5
#define VIA_MAX_CACHELINE_SIZE 64
@@ -114,7 +114,7 @@
#define VIA_MEM_VIDEO 0 /* matches drm constant */
#define VIA_MEM_AGP 1 /* matches drm constant */
-#define VIA_MEM_SYSTEM 2
+#define VIA_MEM_SYSTEM 2
#define VIA_MEM_MIXED 3
#define VIA_MEM_UNKNOWN 4
@@ -203,7 +203,7 @@ typedef struct _drm_via_sarea {
unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
- unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
+ unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
/* Used by the 3d driver only at this point, for pageflipping:
*/
@@ -250,14 +250,14 @@ typedef union drm_via_irqwait {
struct drm_wait_vblank_reply reply;
} drm_via_irqwait_t;
-typedef struct drm_via_blitsync {
+typedef struct drm_via_blitsync {
uint32_t sync_handle;
unsigned engine;
} drm_via_blitsync_t;
-/*
+/*
* Below,"flags" is currently unused but will be used for possible future
- * extensions like kernel space bounce buffers for bad alignments and
+ * extensions like kernel space bounce buffers for bad alignments and
* blit engine busy-wait polling for better latency in the absence of
* interrupts.
*/
@@ -271,11 +271,11 @@ typedef struct drm_via_dmablit {
unsigned char *mem_addr;
uint32_t mem_stride;
-
+
uint32_t flags;
int to_fb;
- drm_via_blitsync_t sync;
+ drm_via_blitsync_t sync;
} drm_via_dmablit_t;
diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h
index 0b474844..d6da8bd9 100644
--- a/shared-core/via_drv.h
+++ b/shared-core/via_drv.h
@@ -83,7 +83,7 @@ typedef struct drm_via_irq {
uint32_t enable_mask;
wait_queue_head_t irq_queue;
} drm_via_irq_t;
-
+
typedef struct drm_via_private {
drm_via_sarea_t *sarea_priv;
drm_local_map_t *sarea;
@@ -110,8 +110,8 @@ typedef struct drm_via_private {
drm_via_irq_t via_irqs[VIA_NUM_IRQS];
unsigned num_irqs;
maskarray_t *irq_masks;
- uint32_t irq_enable_mask;
- uint32_t irq_pending_mask;
+ uint32_t irq_enable_mask;
+ uint32_t irq_pending_mask;
int *irq_map;
/* Memory manager stuff */
#ifdef VIA_HAVE_CORE_MM
@@ -213,7 +213,7 @@ extern int via_init_mem_type(struct drm_device *dev, uint32_t type,
struct drm_mem_type_manager *man);
extern uint32_t via_evict_mask(struct drm_buffer_object *bo);
extern int via_move(struct drm_buffer_object *bo, int evict,
- int no_wait, struct drm_bo_mem_reg *new_mem);
+ int no_wait, struct drm_bo_mem_reg *new_mem);
#endif
#endif
diff --git a/shared-core/via_irq.c b/shared-core/via_irq.c
index 475b6461..df91ab00 100644
--- a/shared-core/via_irq.c
+++ b/shared-core/via_irq.c
@@ -63,7 +63,7 @@
/*
* Device-specific IRQs go here. This type might need to be extended with
* the register if there are multiple IRQ control registers.
- * Currently we activate the HQV interrupts of Unichrome Pro group A.
+ * Currently we activate the HQV interrupts of Unichrome Pro group A.
*/
static maskarray_t via_pro_group_a_irqs[] = {
@@ -71,7 +71,7 @@ static maskarray_t via_pro_group_a_irqs[] = {
0x00000000 },
{VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
0x00000000 },
- {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
+ {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
@@ -81,7 +81,7 @@ static int via_num_pro_group_a =
static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
static maskarray_t via_unichrome_irqs[] = {
- {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
+ {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}
@@ -90,7 +90,7 @@ static int via_num_unichrome = sizeof(via_unichrome_irqs)/sizeof(maskarray_t);
static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
-static unsigned time_diff(struct timeval *now,struct timeval *then)
+static unsigned time_diff(struct timeval *now,struct timeval *then)
{
return (now->tv_usec >= then->tv_usec) ?
now->tv_usec - then->tv_usec :
@@ -117,7 +117,7 @@ irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
microtime(&cur_vblank);
#endif
if (dev_priv->last_vblank_valid) {
- dev_priv->usec_per_vblank =
+ dev_priv->usec_per_vblank =
time_diff(&cur_vblank,
&dev_priv->last_vblank) >> 4;
}
@@ -132,7 +132,7 @@ irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
drm_vbl_send_signals(dev);
handled = 1;
}
-
+
for (i=0; i<dev_priv->num_irqs; ++i) {
if (status & cur_irq->pending_mask) {
atomic_inc( &cur_irq->irq_received );
@@ -148,7 +148,7 @@ irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
}
cur_irq++;
}
-
+
/* Acknowlege interrupts */
VIA_WRITE(VIA_REG_INTERRUPT, status);
@@ -166,7 +166,7 @@ static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)
if (dev_priv) {
/* Acknowlege interrupts */
status = VIA_READ(VIA_REG_INTERRUPT);
- VIA_WRITE(VIA_REG_INTERRUPT, status |
+ VIA_WRITE(VIA_REG_INTERRUPT, status |
dev_priv->irq_pending_mask);
}
}
@@ -193,7 +193,7 @@ int via_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence)
DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
(((cur_vblank = atomic_read(&dev->vbl_received)) -
*sequence) <= (1 << 23)));
-
+
*sequence = cur_vblank;
return ret;
}
@@ -221,7 +221,7 @@ via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequenc
irq);
return -EINVAL;
}
-
+
real_irq = dev_priv->irq_map[irq];
if (real_irq < 0) {
@@ -235,14 +235,14 @@ via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequenc
if (masks[real_irq][2] && !force_sequence) {
DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
- ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
+ ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
masks[irq][4]));
cur_irq_sequence = atomic_read(&cur_irq->irq_received);
} else {
DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
(((cur_irq_sequence =
atomic_read(&cur_irq->irq_received)) -
- *sequence) <= (1 << 23)));
+ *sequence) <= (1 << 23)));
}
*sequence = cur_irq_sequence;
return ret;
@@ -280,23 +280,23 @@ void via_driver_irq_preinstall(struct drm_device * dev)
for(i=0; i < dev_priv->num_irqs; ++i) {
atomic_set(&cur_irq->irq_received, 0);
- cur_irq->enable_mask = dev_priv->irq_masks[i][0];
+ cur_irq->enable_mask = dev_priv->irq_masks[i][0];
cur_irq->pending_mask = dev_priv->irq_masks[i][1];
DRM_INIT_WAITQUEUE( &cur_irq->irq_queue );
dev_priv->irq_enable_mask |= cur_irq->enable_mask;
dev_priv->irq_pending_mask |= cur_irq->pending_mask;
cur_irq++;
-
+
DRM_DEBUG("Initializing IRQ %d\n", i);
}
-
+
dev_priv->last_vblank_valid = 0;
/* Clear VSync interrupt regs */
status = VIA_READ(VIA_REG_INTERRUPT);
- VIA_WRITE(VIA_REG_INTERRUPT, status &
+ VIA_WRITE(VIA_REG_INTERRUPT, status &
~(dev_priv->irq_enable_mask));
-
+
/* Clear bits if they're already high */
viadrv_acknowledge_irqs(dev_priv);
}
@@ -317,7 +317,7 @@ void via_driver_irq_postinstall(struct drm_device * dev)
VIA_WRITE8(0x83d4, 0x11);
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
-
+
}
}
@@ -335,7 +335,7 @@ void via_driver_irq_uninstall(struct drm_device * dev)
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
status = VIA_READ(VIA_REG_INTERRUPT);
- VIA_WRITE(VIA_REG_INTERRUPT, status &
+ VIA_WRITE(VIA_REG_INTERRUPT, status &
~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
}
}
@@ -353,7 +353,7 @@ int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv)
return -EINVAL;
if (irqwait->request.irq >= dev_priv->num_irqs) {
- DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__,
+ DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__,
irqwait->request.irq);
return -EINVAL;
}
@@ -372,7 +372,7 @@ int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv)
}
if (irqwait->request.type & VIA_IRQ_SIGNAL) {
- DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n",
+ DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n",
__FUNCTION__);
return -EINVAL;
}
diff --git a/shared-core/via_map.c b/shared-core/via_map.c
index 1623df68..b8f61673 100644
--- a/shared-core/via_map.c
+++ b/shared-core/via_map.c
@@ -140,4 +140,3 @@ int via_driver_unload(struct drm_device *dev)
return 0;
}
-
diff --git a/shared-core/via_verifier.c b/shared-core/via_verifier.c
index ded5c4e1..cfacd0ca 100644
--- a/shared-core/via_verifier.c
+++ b/shared-core/via_verifier.c
@@ -77,7 +77,7 @@ typedef enum {
/*
* Associates each hazard above with a possible multi-command
* sequence. For example an address that is split over multiple
- * commands and that needs to be checked at the first command
+ * commands and that needs to be checked at the first command
* that does not include any part of the address.
*/
@@ -283,10 +283,10 @@ static __inline__ drm_local_map_t *via_drm_lookup_agp_map(drm_via_state_t * seq,
}
/*
- * Require that all AGP texture levels reside in the same AGP map which should
+ * Require that all AGP texture levels reside in the same AGP map which should
* be mappable by the client. This is not a big restriction.
- * FIXME: To actually enforce this security policy strictly, drm_rmmap
- * would have to wait for dma quiescent before removing an AGP map.
+ * FIXME: To actually enforce this security policy strictly, drm_rmmap
+ * would have to wait for dma quiescent before removing an AGP map.
* The via_drm_lookup_agp_map call in reality seems to take
* very little CPU time.
*/
@@ -451,15 +451,15 @@ investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t * cur_seq)
case check_texture_addr3:
cur_seq->unfinished = tex_address;
tmp = ((cmd >> 24) - HC_SubA_HTXnL0Pit);
- if (tmp == 0 &&
+ if (tmp == 0 &&
(cmd & HC_HTXnEnPit_MASK)) {
- cur_seq->pitch[cur_seq->texture][tmp] =
+ cur_seq->pitch[cur_seq->texture][tmp] =
(cmd & HC_HTXnLnPit_MASK);
cur_seq->tex_npot[cur_seq->texture] = 1;
} else {
cur_seq->pitch[cur_seq->texture][tmp] =
(cmd & HC_HTXnLnPitE_MASK) >> HC_HTXnLnPitE_SHIFT;
- cur_seq->tex_npot[cur_seq->texture] = 0;
+ cur_seq->tex_npot[cur_seq->texture] = 0;
if (cmd & 0x000FFFFF) {
DRM_ERROR
("Unimplemented texture level 0 pitch mode.\n");
@@ -1007,7 +1007,7 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size,
state = via_check_vheader6(&buf, buf_end);
break;
case state_command:
- if ((HALCYON_HEADER2 == (cmd = *buf)) &&
+ if ((HALCYON_HEADER2 == (cmd = *buf)) &&
supported_3d)
state = state_header2;
else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
diff --git a/shared-core/via_verifier.h b/shared-core/via_verifier.h
index dac1db91..c50a8130 100644
--- a/shared-core/via_verifier.h
+++ b/shared-core/via_verifier.h
@@ -27,7 +27,7 @@
#define _VIA_VERIFIER_H_
typedef enum {
- no_sequence = 0,
+ no_sequence = 0,
z_address,
dest_address,
tex_address
@@ -37,12 +37,12 @@ typedef enum {
typedef struct {
unsigned texture;
- uint32_t z_addr;
- uint32_t d_addr;
+ uint32_t z_addr;
+ uint32_t d_addr;
uint32_t t_addr[2][10];
uint32_t pitch[2][10];
uint32_t height[2][10];
- uint32_t tex_level_lo[2];
+ uint32_t tex_level_lo[2];
uint32_t tex_level_hi[2];
uint32_t tex_palette_size[2];
uint32_t tex_npot[2];
@@ -56,7 +56,7 @@ typedef struct {
const uint32_t *buf_start;
} drm_via_state_t;
-extern int via_verify_command_stream(const uint32_t * buf, unsigned int size,
+extern int via_verify_command_stream(const uint32_t * buf, unsigned int size,
struct drm_device *dev, int agp);
extern int via_parse_command_stream(struct drm_device *dev, const uint32_t * buf,
unsigned int size);
diff --git a/shared-core/xgi_drm.h b/shared-core/xgi_drm.h
index de0fb532..ce584420 100644
--- a/shared-core/xgi_drm.h
+++ b/shared-core/xgi_drm.h
@@ -62,14 +62,14 @@ enum xgi_mem_location {
struct xgi_mem_alloc {
/**
* Memory region to be used for allocation.
- *
+ *
* Must be one of XGI_MEMLOC_NON_LOCAL or XGI_MEMLOC_LOCAL.
*/
unsigned int location;
/**
* Number of bytes request.
- *
+ *
* On successful allocation, set to the actual number of bytes
* allocated.
*/
@@ -87,7 +87,7 @@ struct xgi_mem_alloc {
/**
* Magic handle used to release memory.
- *
+ *
* See also DRM_XGI_FREE ioctl.
*/
__u32 index;