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authorXiang, Haihao <haihao.xiang@intel.com>2008-03-28 17:32:45 +0800
committerXiang, Haihao <haihao.xiang@intel.com>2008-03-28 17:32:45 +0800
commit184cf464f4183a664fa0358fe118735e6fd98afe (patch)
treef57b3a123d0bff5f470ef3f41eda879bbe344208
parent6054788f3620b4fc8ba386b38546ae2cc9dd24d2 (diff)
i965: depth offset on glPolygonMode(GL_LINE/GL_POINT)
-rw-r--r--src/mesa/drivers/dri/i965/brw_clip_unfilled.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
index 918e000187..57ebf388f5 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
@@ -220,8 +220,8 @@ static void apply_one_offset( struct brw_clip_compile *c,
struct brw_indirect vert )
{
struct brw_compile *p = &c->func;
- struct brw_reg pos = deref_4f(vert, c->offset[VERT_RESULT_HPOS]);
- struct brw_reg z = get_element(pos, 2);
+ struct brw_reg z = deref_1f(vert, c->header_position_offset +
+ 2 * type_sz(BRW_REGISTER_TYPE_F));
brw_ADD(p, z, z, vec1(c->reg.offset));
}