diff options
| author | Eric Anholt <eric@anholt.net> | 2009-05-14 09:49:45 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-05-14 11:41:04 -0700 |
| commit | 0f5113deed91611ecdda6596542530b1849bb161 (patch) | |
| tree | 13c1ec27d8b7c8d0675ef9f8f674d649f8eb345a /src/mesa/drivers/dri/i965/brw_wm.c | |
| parent | 64980125c76b05501a6fe7fe20fe52438f459129 (diff) | |
i965: Fix register allocation of GLSL fp inputs.
Before, if the VP output something that is in the attributes coming into
the WM but which isn't used by the WM, then WM would end up reading subsequent
varyings from the wrong places. This was visible with a GLSL demo
using gl_PointSize in the VS and a varying in the WM, as point size is in
the VUE but not used by the WM. There is now a regression test in piglit,
glsl-unused-varying.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index cd65f57bbc..3e476fd3be 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -319,6 +319,9 @@ static void brw_wm_populate_key( struct brw_context *brw, key->drawable_height = brw->intel.driDrawable->h; } + /* CACHE_NEW_VS_PROG */ + key->vp_outputs_written = brw->vs.prog_data->outputs_written & DO_SETUP_BITS; + /* The unique fragment program ID */ key->program_string_id = fp->id; } @@ -357,7 +360,7 @@ const struct brw_tracked_state brw_wm_prog = { .brw = (BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_WM_INPUT_DIMENSIONS | BRW_NEW_REDUCED_PRIMITIVE), - .cache = 0 + .cache = CACHE_NEW_VS_PROG, }, .prepare = brw_prepare_wm_prog }; |