diff options
| author | Wang Zhenyu <zhenyu.z.wang@intel.com> | 2007-05-30 16:03:50 +0800 |
|---|---|---|
| committer | Keith Whitwell <keith@tungstengraphics.com> | 2007-05-31 11:18:14 +0100 |
| commit | 1b27ef39c9abeaa03d65f477ac4538361f2341cc (patch) | |
| tree | 1f81a2ae5913e8165b449c2d8d2dbb8bedadbe52 /src/mesa/drivers/dri/i965 | |
| parent | 2b7ef2549f017996073f51bc147f508c325a1db6 (diff) | |
i965: Add pci info for 965GME/GLE chip.
Diffstat (limited to 'src/mesa/drivers/dri/i965')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_context.c | 13 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_context.h | 1 |
2 files changed, 9 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c index 10eb9a2e28..4f51fefe0f 100644 --- a/src/mesa/drivers/dri/i965/intel_context.c +++ b/src/mesa/drivers/dri/i965/intel_context.c @@ -106,20 +106,23 @@ static const GLubyte *intelGetString( GLcontext *ctx, GLenum name ) case GL_RENDERER: switch (intel_context(ctx)->intelScreen->deviceID) { case PCI_CHIP_I965_Q: - chipset = "Intel(R) 965Q"; break; + chipset = "Intel(R) 965Q"; break; case PCI_CHIP_I965_G: case PCI_CHIP_I965_G_1: - chipset = "Intel(R) 965G"; break; + chipset = "Intel(R) 965G"; break; case PCI_CHIP_I946_GZ: - chipset = "Intel(R) 946GZ"; break; + chipset = "Intel(R) 946GZ"; break; case PCI_CHIP_I965_GM: - chipset = "Intel(R) 965GM"; break; + chipset = "Intel(R) 965GM"; + break; + case PCI_CHIP_I965_GME: + chipset = "Intel(R) 965GME/GLE"; break; default: - chipset = "Unknown Intel Chipset"; break; + chipset = "Unknown Intel Chipset"; } (void) driGetRendererString( buffer, chipset, DRIVER_VERSION, 0 ); diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h index a3c65b66e0..406f8483dc 100644 --- a/src/mesa/drivers/dri/i965/intel_context.h +++ b/src/mesa/drivers/dri/i965/intel_context.h @@ -385,6 +385,7 @@ extern int INTEL_DEBUG; #define PCI_CHIP_I965_G_1 0x2982 #define PCI_CHIP_I946_GZ 0x2972 #define PCI_CHIP_I965_GM 0x2A02 +#define PCI_CHIP_I965_GME 0x2A12 /* ================================================================ |