diff options
author | Nicolai Hähnle <nhaehnle@gmail.com> | 2009-10-03 21:28:59 +0200 |
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committer | Nicolai Hähnle <nhaehnle@gmail.com> | 2009-10-03 23:37:16 +0200 |
commit | b7cf887ca74561469c144f1d12227e1bcf277e7e (patch) | |
tree | c956777f799712573febf464310a1ec0f75f1991 /src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h | |
parent | 6d25b9125ec1e66e0e255b0ee20fe18dfe1076fa (diff) |
r300/compiler: Introduce control flow instructions and refactor dataflow
Note that control flow instruction support isn't actually fully functional yet.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h')
-rw-r--r-- | src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h index 8e30bef1e3..f8ba5255ca 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h @@ -166,6 +166,18 @@ typedef enum { RC_OPCODE_TXL, RC_OPCODE_TXP, + /** branch instruction: + * If src0.x != 0.0, continue with the next instruction; + * otherwise, jump to matching RC_OPCODE_ELSE or RC_OPCODE_ENDIF. + */ + RC_OPCODE_IF, + + /** branch instruction: jump to matching RC_OPCODE_ENDIF */ + RC_OPCODE_ELSE, + + /** branch instruction: has no effect */ + RC_OPCODE_ENDIF, + /** special instruction, used in R300-R500 fragment program pair instructions * indicates that the result of the alpha operation shall be replicated * across all other channels */ @@ -188,6 +200,9 @@ struct rc_opcode_info { unsigned int NumSrcRegs:2; unsigned int HasDstReg:1; + /** true if this instruction affects control flow */ + unsigned int IsControlFlow:1; + /** true if this is a vector instruction that operates on components in parallel * without any cross-component interaction */ unsigned int IsComponentwise:1; @@ -207,4 +222,9 @@ static inline const struct rc_opcode_info * rc_get_opcode_info(rc_opcode opcode) return &rc_opcodes[opcode]; } +void rc_compute_sources_for_writemask( + const struct rc_opcode_info * opcode, + unsigned int writemask, + unsigned int *srcmasks); + #endif /* RADEON_OPCODES_H */ |