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| author | Maciej Cencora <m.cencora@gmail.com> | 2009-05-02 17:27:03 +0200 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2009-05-04 12:09:36 -0400 |
| commit | 0b22615c2c860968a027c04519e25864ae69f6cd (patch) | |
| tree | 88ea6ba2f202f49dcf70335dc6097027da3b38c2 /src/mesa/drivers/dri/radeon/radeon_common_context.c | |
| parent | 55db6ce537f1fd9acf205400202abfcc3908d6c3 (diff) | |
r300: set proper texture row alignment for IGP chips
Looks like r400 based IGP chips require 64 byte alignment
Diffstat (limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.c')
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_common_context.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index ba74c97f2c..3e713628ec 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -177,6 +177,8 @@ GLboolean radeonInitContext(radeonContextPtr radeon, radeon->texture_depth = ( glVisual->rgbBits > 16 ) ? DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; + radeon->texture_row_align = 32; + return GL_TRUE; } |