Adjustments to make everything use IOCTL/sarea defines in DRM instead

of glx/mini. removes glx/mini/drm.h glx/mini/sarea.h

1 files changed, 5 insertions, 5 deletions

diff --git a/src/mesa/drivers/dri/radeon/radeon_texmem.c b/src/mesa/drivers/dri/radeon/radeon_texmem.c
index c985267d6b..61f187762c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texmem.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texmem.c
@@ -183,8 +183,8 @@ static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t,
    GLuint offset;
    GLint imageWidth, imageHeight;
    GLint ret;
-   drmRadeonTexture tex;
-   drmRadeonTexImage tmp;
+   drm_radeon_texture_t tex;
+   drm_radeon_tex_image_t tmp;
    const int level = hwlevel + t->base.firstLevel;
 
    if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
@@ -245,7 +245,7 @@ static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t,
 
    t->image[face][hwlevel].data = texImage->Data;
 
-   /* Init the DRM_RADEON_TEXTURE command / drmRadeonTexture struct.
+   /* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct.
     * NOTE: we're always use a 1KB-wide blit and I8 texture format.
     * We used to use 1, 2 and 4-byte texels and used to use the texture
     * width to dictate the blit width - but that won't work for compressed
@@ -267,12 +267,12 @@ static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t,
    tex.image = &tmp;
 
    /* copy (x,y,width,height,data) */
-   memcpy( &tmp, &t->image[face][hwlevel], sizeof(drmRadeonTexImage) );
+   memcpy( &tmp, &t->image[face][hwlevel], sizeof(drm_radeon_tex_image_t) );
 
    LOCK_HARDWARE( rmesa );
    do {
       ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_TEXTURE,
-                                 &tex, sizeof(drmRadeonTexture) );
+                                 &tex, sizeof(drm_radeon_texture_t) );
    } while ( ret && errno == EAGAIN );
 
    UNLOCK_HARDWARE( rmesa );