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authorEric Anholt <eric@anholt.net>2008-06-17 11:15:59 -0700
committerEric Anholt <eric@anholt.net>2008-06-17 11:18:02 -0700
commite2baf564d1b9716611d194cf117b329a92ad603d (patch)
treeaefc5890f2f80c9ddbd31ac0809a8baa635cd961 /src/mesa
parent407ce3da3c53c9ebba0fbf827d7b0f610122d44b (diff)
[intel-gem] Bug #16326: Fix X tile unswizzling on 965.
Apparently a bit gets flipped in the addressing for some rows of each tile.
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/intel/intel_span.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 149b581d88..c6778b16ff 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -106,12 +106,38 @@ static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
x_tile_off = xbyte & 0x1ff;
y_tile_off = y & 7;
+#ifndef I915
+ /* The documentation says that X tile layout is arranged in 8 512-byte
+ * lines of pixel data. However, that doesn't appear to be the case
+ * on GM965, tested by drawing a 128x8 quad in no_rast mode. For lines
+ * 1,2,4, and 7 of each tile, each consecutive pair of 64-byte spans
+ * has the locations of those spans swapped.
+ */
+ switch (y_tile_off) {
+ case 1:
+ case 2:
+ case 4:
+ case 7:
+ x_tile_off ^= 64;
+ break;
+ default:
+ break;
+ }
+#endif
+
x_tile_number = xbyte >> 9;
y_tile_number = y >> 3;
tile_off = (y_tile_off << 9) + x_tile_off;
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
+#if 0
+ printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
+ x, y, tile_off, tile_base,
+ tile_off + tile_base,
+ irb->pfPitch, tile_stride);
+#endif
+
return buf + tile_base + tile_off;
}