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authorBrian Paul <brian.paul@tungstengraphics.com>2008-09-08 11:53:14 -0600
committerBrian Paul <brian.paul@tungstengraphics.com>2008-09-11 10:39:28 -0600
commit04ae4fba3c0a656cf2747fc994b99f99576d0e2b (patch)
treee2dd9e237775ab5e7282ea2b1ca0f4f1c2fec121 /src
parentcd9722dcddcb41af3196860280d23542dc673700 (diff)
cell: minor change to Z float/int conversion code (avoid switch)
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/cell/spu/spu_main.c5
-rw-r--r--src/gallium/drivers/cell/spu/spu_main.h5
-rw-r--r--src/gallium/drivers/cell/spu/spu_per_fragment_op.c34
3 files changed, 23 insertions, 21 deletions
diff --git a/src/gallium/drivers/cell/spu/spu_main.c b/src/gallium/drivers/cell/spu/spu_main.c
index d223f32d94..c4236817a9 100644
--- a/src/gallium/drivers/cell/spu/spu_main.c
+++ b/src/gallium/drivers/cell/spu/spu_main.c
@@ -252,12 +252,17 @@ cmd_state_framebuffer(const struct cell_command_framebuffer *cmd)
switch (spu.fb.depth_format) {
case PIPE_FORMAT_Z32_UNORM:
+ spu.fb.zsize = 4;
+ spu.fb.zscale = (float) 0xffffffffu;
+ break;
case PIPE_FORMAT_Z24S8_UNORM:
case PIPE_FORMAT_S8Z24_UNORM:
spu.fb.zsize = 4;
+ spu.fb.zscale = (float) 0x00ffffffu;
break;
case PIPE_FORMAT_Z16_UNORM:
spu.fb.zsize = 2;
+ spu.fb.zscale = (float) 0xffffu;
break;
default:
spu.fb.zsize = 0;
diff --git a/src/gallium/drivers/cell/spu/spu_main.h b/src/gallium/drivers/cell/spu/spu_main.h
index 4879f8c9c8..c2a53c9dcf 100644
--- a/src/gallium/drivers/cell/spu/spu_main.h
+++ b/src/gallium/drivers/cell/spu/spu_main.h
@@ -41,6 +41,10 @@
#define MAX_HEIGHT 1024
+/**
+ * A tile is basically a TILE_SIZE x TILE_SIZE block of 4-byte pixels.
+ * The data may be addressed through several different types.
+ */
typedef union {
ushort us[TILE_SIZE][TILE_SIZE];
uint ui[TILE_SIZE][TILE_SIZE];
@@ -99,6 +103,7 @@ struct spu_framebuffer {
uint depth_clear_value;
uint zsize; /**< 0, 2 or 4 bytes per Z */
+ float zscale; /**< 65535.0, 2^24-1 or 2^32-1 */
} ALIGN16_ATTRIB;
diff --git a/src/gallium/drivers/cell/spu/spu_per_fragment_op.c b/src/gallium/drivers/cell/spu/spu_per_fragment_op.c
index db88735226..29dc07a2e8 100644
--- a/src/gallium/drivers/cell/spu/spu_per_fragment_op.c
+++ b/src/gallium/drivers/cell/spu/spu_per_fragment_op.c
@@ -144,18 +144,22 @@ write_ds_quad(tile_t *buffer, unsigned x, unsigned y,
case PIPE_FORMAT_Z24S8_UNORM: {
qword *ptr = (qword *) &buffer->ui4[iy][ix];
+ /* form select mask = 1110,1110,1110,1110 */
qword mask = si_fsmbi(0xEEEE);
-
+ /* depth[i] = depth[i] << 8 */
depth = si_shli(depth, 8);
+ /* *ptr[i] = depth[i][31:8] | stencil[i][7:0] */
*ptr = si_selb(stencil, depth, mask);
break;
}
case PIPE_FORMAT_S8Z24_UNORM: {
qword *ptr = (qword *) &buffer->ui4[iy][ix];
+ /* form select mask = 0111,0111,0111,0111 */
qword mask = si_fsmbi(0x7777);
-
+ /* stencil[i] = stencil[i] << 24 */
stencil = si_shli(stencil, 24);
+ /* *ptr[i] = stencil[i][31:24] | depth[i][23:0] */
*ptr = si_selb(stencil, depth, mask);
break;
}
@@ -191,25 +195,13 @@ spu_do_depth_stencil(int x, int y,
read_ds_quad(&spu.ztile, x, y, spu.fb.depth_format,
&pixel_depth, &pixel_stencil);
}
-
- switch (spu.fb.depth_format) {
- case PIPE_FORMAT_Z16_UNORM:
- frag_depth = si_fm(frag_depth, (qword)spu_splats((float)(0x0000ffffu)));
- frag_depth = si_cfltu(frag_depth, 0);
- break;
- case PIPE_FORMAT_Z32_UNORM:
- frag_depth = si_fm(frag_depth, (qword)spu_splats((float)(0xffffffffu)));
- frag_depth = si_cfltu(frag_depth, 0);
- break;
- case PIPE_FORMAT_Z24S8_UNORM:
- case PIPE_FORMAT_S8Z24_UNORM:
- frag_depth = si_fm(frag_depth, (qword)spu_splats((float)(0x00ffffffu)));
- frag_depth = si_cfltu(frag_depth, 0);
- break;
- default:
- ASSERT(0);
- break;
- }
+
+ /* convert floating point Z values to 32-bit uint */
+
+ /* frag_depth *= spu.fb.zscale */
+ frag_depth = si_fm(frag_depth, (qword)spu_splats(spu.fb.zscale));
+ /* frag_depth = uint(frag_depth) */
+ frag_depth = si_cfltu(frag_depth, 0);
result = (*spu.frag_test)(frag_mask, pixel_depth, pixel_stencil,
frag_depth, frag_alpha, facing);