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authorAlex Deucher <alexdeucher@gmail.com>2009-07-29 15:15:36 -0400
committerAlex Deucher <alexdeucher@gmail.com>2009-07-29 17:25:56 -0400
commit1e207ba9c127d12feff3e1c2e8e29da26182e0bb (patch)
tree933e9787de559fd6b5e88e467dfd9671c3abcc43 /src
parent0723cd1b0a8a76808844a2216d709f56fbad88e2 (diff)
r600: minor fixes
- set MAX_LOD properly - min texel pitch is 8 texels - emit old command buffer when re-initing base state
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/r600/r600_tex.c2
-rw-r--r--src/mesa/drivers/dri/r600/r600_texstate.c13
-rw-r--r--src/mesa/drivers/dri/r600/r700_state.c3
3 files changed, 16 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c
index 853f824b2c..6d531bf0f9 100644
--- a/src/mesa/drivers/dri/r600/r600_tex.c
+++ b/src/mesa/drivers/dri/r600/r600_tex.c
@@ -160,7 +160,7 @@ static void r600SetTexDefaultState(radeonTexObjPtr t)
SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_BORDER_COLOR_TRANS_BLACK, BORDER_COLOR_TYPE_shift, BORDER_COLOR_TYPE_mask);
t->SQ_TEX_SAMPLER1 = 0;
- SETfield(t->SQ_TEX_SAMPLER1, MAX_LOD_mask, MAX_LOD_shift, MAX_LOD_mask);
+ SETfield(t->SQ_TEX_SAMPLER1, 0x3ff, MAX_LOD_shift, MAX_LOD_mask);
t->SQ_TEX_SAMPLER2 = 0;
SETbit(t->SQ_TEX_SAMPLER2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index 1cf3b484ae..70dd540481 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -598,6 +598,10 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
uTexelPitch = (firstImage->Width + R700_TEXEL_PITCH_ALIGNMENT_MASK)
& ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
+ /* min pitch is 8 */
+ if (uTexelPitch < 8)
+ uTexelPitch = 8;
+
SETfield(t->SQ_TEX_RESOURCE0, (uTexelPitch/8)-1, PITCH_shift, PITCH_mask);
SETfield(t->SQ_TEX_RESOURCE0, firstImage->Width - 1,
TEX_WIDTH_shift, TEX_WIDTH_mask);
@@ -751,6 +755,11 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
& ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
+
+ /* min pitch is 8 */
+ if (pitch_val < 8)
+ pitch_val = 8;
+
SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask);
}
@@ -898,6 +907,10 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
& ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
+ /* min pitch is 8 */
+ if (pitch_val < 8)
+ pitch_val = 8;
+
SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask);
SETfield(t->SQ_TEX_RESOURCE0, rb->base.Width - 1,
TEX_WIDTH_shift, TEX_WIDTH_mask);
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 87ea1719c4..e0a5742591 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -1638,9 +1638,10 @@ static void r700InitSQConfig(GLcontext * ctx)
void r700InitState(GLcontext * ctx) //-------------------
{
context_t *context = R700_CONTEXT(ctx);
-
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+ radeon_firevertices(&context->radeon);
+
r700->TA_CNTL_AUX.u32All = 0;
SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
r700->VC_ENHANCE.u32All = 0;