summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorEric Anholt <eric@anholt.net>2009-06-12 08:44:40 -0700
committerEric Anholt <eric@anholt.net>2009-06-17 20:19:19 -0700
commitbd10f0e84f1491363d76d92dcbd410ab5cc43dbe (patch)
tree5ffeada7cd79fc5f507e4e6ab1779d3fa8058f27 /src
parentb165fa7d45e230f9e61fcf3a09babf0c61c67319 (diff)
i965: Fix tiling for FBO depth attachments by making DEPTH_COMPONENT Y tiled.
This may hurt if miptree relayout occurs, since we can't blit Y tiled objects. But it corrects depth tests on FBOs using textures.
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/intel/intel_mipmap_tree.c10
-rw-r--r--src/mesa/drivers/dri/intel/intel_regions.c2
2 files changed, 8 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 0d34f28311..fcfed9e751 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -113,9 +113,13 @@ intel_miptree_create(struct intel_context *intel,
uint32_t tiling;
if (intel->use_texture_tiling && compress_byte == 0 &&
- intel->intelScreen->kernel_exec_fencing)
- tiling = I915_TILING_X;
- else
+ intel->intelScreen->kernel_exec_fencing) {
+ if (IS_965(intel->intelScreen->deviceID) &&
+ internal_format == GL_DEPTH_COMPONENT)
+ tiling = I915_TILING_Y;
+ else
+ tiling = I915_TILING_X;
+ } else
tiling = I915_TILING_NONE;
mt = intel_miptree_create_internal(intel, target, internal_format,
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 49bcb3c1dd..7c3b483836 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -189,7 +189,7 @@ intel_region_alloc(struct intel_context *intel,
pitch, buffer);
if (tiling != I915_TILING_NONE) {
- assert(((pitch * cpp) & 511) == 0);
+ assert(((pitch * cpp) & 127) == 0);
drm_intel_bo_set_tiling(buffer, &tiling, pitch * cpp);
drm_intel_bo_get_tiling(buffer, &region->tiling, &region->bit_6_swizzle);
}