diff options
| -rw-r--r-- | src/mesa/drivers/dri/r600/r600_blit.c | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r600/r700_render.c | 5 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c index d7cd59ade6..4bb77a398f 100644 --- a/src/mesa/drivers/dri/r600/r600_blit.c +++ b/src/mesa/drivers/dri/r600/r600_blit.c @@ -1652,6 +1652,7 @@ unsigned r600_blit(GLcontext *ctx, CB_ACTION_ENA_bit | (1 << (id + 6))); /* 5 */ + /* XXX drm should handle this in fence submit */ r700WaitForIdleClean(context); radeonFlush(ctx); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 96c12ce544..8f14af7472 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -115,8 +115,6 @@ void r700Start3D(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700WaitForIdleClean(context); } GLboolean r700SyncSurf(context_t *context, @@ -421,7 +419,7 @@ static void r700RunRenderPrimitiveImmediate(GLcontext * ctx, int start, int end, } /* start 3d, idle, cb/db flush */ -#define PRE_EMIT_STATE_BUFSZ 10 + 5 + 18 +#define PRE_EMIT_STATE_BUFSZ 5 + 5 + 18 static GLuint r700PredictRenderSize(GLcontext* ctx, const struct _mesa_prim *prim, @@ -934,6 +932,7 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, radeon_debug_remove_indent(); /* Flush render op cached for last several quads. */ + /* XXX drm should handle this in fence submit */ r700WaitForIdleClean(context); rrb = radeon_get_colorbuffer(&context->radeon); |