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path: root/src/mesa/drivers/dri/i965/brw_wm_pass2.c
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Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_pass2.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_pass2.c21
1 files changed, 11 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 780edbc42e..6faea018fb 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -69,8 +69,6 @@ static void prealloc_reg(struct brw_wm_compile *c,
*/
static void init_registers( struct brw_wm_compile *c )
{
- struct brw_context *brw = c->func.brw;
- GLuint inputs = (brw->vs.prog_data->outputs_written & DO_SETUP_BITS);
GLuint nr_interp_regs = 0;
GLuint i = 0;
GLuint j;
@@ -85,16 +83,19 @@ static void init_registers( struct brw_wm_compile *c )
prealloc_reg(c, &c->creg[j], i++);
for (j = 0; j < FRAG_ATTRIB_MAX; j++) {
- if (inputs & (1<<j)) {
- /* index for vs output and ps input are not the same
- in shader varying */
- GLuint index;
- if (j > FRAG_ATTRIB_VAR0)
- index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+ if (c->key.vp_outputs_written & (1<<j)) {
+ int fp_index;
+
+ if (j >= VERT_RESULT_VAR0)
+ fp_index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+ else if (j <= VERT_RESULT_TEX7)
+ fp_index = j;
else
- index = j;
+ fp_index = -1;
+
nr_interp_regs++;
- prealloc_reg(c, &c->payload.input_interp[index], i++);
+ if (fp_index >= 0)
+ prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
}
}