diff options
Diffstat (limited to 'src/mesa/drivers/dri/r200')
-rw-r--r-- | src/mesa/drivers/dri/r200/.gitignore | 14 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r200/Makefile | 10 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r200/r200_cmdbuf.c | 8 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r200/r200_context.c | 5 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r200/r200_ioctl.c | 12 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r200/r200_state.c | 53 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r200/r200_state_init.c | 42 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r200/r200_texstate.c | 6 |
8 files changed, 113 insertions, 37 deletions
diff --git a/src/mesa/drivers/dri/r200/.gitignore b/src/mesa/drivers/dri/r200/.gitignore index 3773d8ea73..2f9cd1a987 100644 --- a/src/mesa/drivers/dri/r200/.gitignore +++ b/src/mesa/drivers/dri/r200/.gitignore @@ -1,3 +1,15 @@ +radeon_bocs_wrapper.h +radeon_bo_legacy.[ch] radeon_chipset.h -radeon_screen.* +radeon_cmdbuf.h +radeon_common.[ch] +radeon_common_context.[ch] +radeon_cs_legacy.[ch] +radeon_dma.[ch] +radeon_fbo.c +radeon_lock.[ch] +radeon_mipmap_tree.[ch] +radeon_screen.[ch] +radeon_span.[ch] +radeon_texture.[ch] server diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index 6a246edf7c..4686241957 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -13,6 +13,10 @@ ifeq ($(USING_EGL), 1) EGL_SOURCES = server/radeon_egl.c endif +ifeq ($(RADEON_LDFLAGS),) +CS_SOURCES = radeon_cs_space_drm.c +endif + RADEON_COMMON_SOURCES = \ radeon_texture.c \ radeon_common_context.c \ @@ -42,7 +46,8 @@ DRIVER_SOURCES = r200_context.c \ r200_vertprog.c \ radeon_screen.c \ $(EGL_SOURCES) \ - $(RADEON_COMMON_SOURCES) + $(RADEON_COMMON_SOURCES) \ + $(CS_SOURCES) C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES) @@ -82,7 +87,8 @@ COMMON_SYMLINKS = \ radeon_texture.h \ radeon_dma.c \ radeon_dma.h \ - radeon_fbo.c + radeon_fbo.c \ + $(CS_SOURCES) DRI_LIB_DEPS += $(RADEON_LDFLAGS) diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index df9dd83344..25e30eda52 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -225,6 +225,7 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint min_nr ) { GLushort *retval; + int ret; if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive); @@ -239,10 +240,11 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, rmesa->radeon.tcl.elt_dma_offset = 0; rmesa->tcl.elt_used = min_nr * 2; - radeon_validate_bo(&rmesa->radeon, rmesa->radeon.tcl.elt_dma_bo, - RADEON_GEM_DOMAIN_GTT, 0); - if (radeon_revalidate_bos(rmesa->radeon.glCtx) == GL_FALSE) + ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, rmesa->radeon.tcl.elt_dma_bo, + RADEON_GEM_DOMAIN_GTT, 0); + if (ret) { fprintf(stderr,"failure to revalidate BOs - badness\n"); + } radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1); retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset; diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 8924849d08..9a92a32079 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -357,6 +357,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, /* FIXME: When no memory manager is available we should set this * to some reasonable value based on texture memory pool size */ ctx->Const.MaxTextureLevels = 12; + ctx->Const.Max3DTextureLevels = 9; + ctx->Const.MaxCubeTextureLevels = 12; + ctx->Const.MaxTextureRectSize = 2048; ctx->Const.MaxTextureMaxAnisotropy = 16.0; @@ -388,6 +391,8 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, ctx->Const.MaxDrawBuffers = 1; + _mesa_set_mvp_with_dp4( ctx, GL_TRUE ); + /* Initialize the software rasterizer and helper modules. */ _swrast_CreateContext( ctx ); diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 0b3398a730..4dbda39eb9 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -58,11 +58,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R200_TIMEOUT 512 #define R200_IDLE_RETRY 16 -static void r200UserClear(GLcontext *ctx, GLuint mask) -{ - radeon_clear_tris(ctx, mask); -} - static void r200KernelClear(GLcontext *ctx, GLuint flags) { r200ContextPtr rmesa = R200_CONTEXT(ctx); @@ -196,7 +191,10 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) GLuint orig_mask = mask; if ( R200_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "r200Clear %x %d\n", mask, rmesa->radeon.sarea->pfCurrentPage); + if (rmesa->radeon.sarea) + fprintf( stderr, "r200Clear %x %d\n", mask, rmesa->radeon.sarea->pfCurrentPage); + else + fprintf( stderr, "r200Clear %x radeon->sarea is NULL\n", mask); } { @@ -250,7 +248,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) } if (rmesa->radeon.radeonScreen->kernel_mm) - r200UserClear(ctx, orig_mask); + radeonUserClear(ctx, orig_mask); else { r200KernelClear(ctx, flags); rmesa->radeon.hw.all_dirty = GL_TRUE; diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index f8ebe0df57..5a6fd20d8c 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -574,6 +574,10 @@ static void r200FrontFace( GLcontext *ctx, GLenum mode ) R200_STATECHANGE( rmesa, tcl ); rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_CULL_FRONT_IS_CCW; + /* Winding is inverted when rendering to FBO */ + if (ctx->DrawBuffer && ctx->DrawBuffer->Name) + mode = (mode == GL_CW) ? GL_CCW : GL_CW; + switch ( mode ) { case GL_CW: rmesa->hw.set.cmd[SET_SE_CNTL] |= R200_FFACE_CULL_CW; @@ -709,14 +713,20 @@ static void r200ColorMask( GLcontext *ctx, GLboolean b, GLboolean a ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint mask = radeonPackColor( rmesa->radeon.radeonScreen->cpp, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP] ); - + GLuint mask; + struct radeon_renderbuffer *rrb; GLuint flag = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & ~R200_PLANE_MASK_ENABLE; + rrb = radeon_get_colorbuffer(&rmesa->radeon); + if (!rrb) + return; + mask = radeonPackColor( rrb->cpp, + ctx->Color.ColorMask[RCOMP], + ctx->Color.ColorMask[GCOMP], + ctx->Color.ColorMask[BCOMP], + ctx->Color.ColorMask[ACOMP] ); + + if (!(r && g && b && a)) flag |= R200_PLANE_MASK_ENABLE; @@ -1720,11 +1730,16 @@ static void r200ClearColor( GLcontext *ctx, const GLfloat c[4] ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); GLubyte color[4]; + struct radeon_renderbuffer *rrb; + + rrb = radeon_get_colorbuffer(&rmesa->radeon); + if (!rrb) + return; CLAMPED_FLOAT_TO_UBYTE(color[0], c[0]); CLAMPED_FLOAT_TO_UBYTE(color[1], c[1]); CLAMPED_FLOAT_TO_UBYTE(color[2], c[2]); CLAMPED_FLOAT_TO_UBYTE(color[3], c[3]); - rmesa->radeon.state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp, + rmesa->radeon.state.color.clear = radeonPackColor( rrb->cpp, color[0], color[1], color[2], color[3] ); } @@ -2274,23 +2289,23 @@ static GLboolean r200ValidateBuffers(GLcontext *ctx) { r200ContextPtr rmesa = R200_CONTEXT(ctx); struct radeon_renderbuffer *rrb; - int i; + int i, ret; - radeon_validate_reset_bos(&rmesa->radeon); + radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs); rrb = radeon_get_colorbuffer(&rmesa->radeon); /* color buffer */ if (rrb && rrb->bo) { - radeon_validate_bo(&rmesa->radeon, rrb->bo, - 0, RADEON_GEM_DOMAIN_VRAM); + radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, rrb->bo, + 0, RADEON_GEM_DOMAIN_VRAM); } /* depth buffer */ rrb = radeon_get_depthbuffer(&rmesa->radeon); /* color buffer */ if (rrb && rrb->bo) { - radeon_validate_bo(&rmesa->radeon, rrb->bo, - 0, RADEON_GEM_DOMAIN_VRAM); + radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, rrb->bo, + 0, RADEON_GEM_DOMAIN_VRAM); } for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { @@ -2301,17 +2316,17 @@ static GLboolean r200ValidateBuffers(GLcontext *ctx) t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); if (t->image_override && t->bo) - radeon_validate_bo(&rmesa->radeon, t->bo, + radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, t->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); else if (t->mt->bo) - radeon_validate_bo(&rmesa->radeon, t->mt->bo, + radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, t->mt->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); } - if (rmesa->radeon.dma.current) - radeon_validate_bo(&rmesa->radeon, rmesa->radeon.dma.current, RADEON_GEM_DOMAIN_GTT, 0); - - return radeon_revalidate_bos(ctx); + ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, rmesa->radeon.dma.current, RADEON_GEM_DOMAIN_GTT, 0); + if (ret) + return GL_FALSE; + return GL_TRUE; } GLboolean r200ValidateState( GLcontext *ctx ) diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 8392009337..bc871d9904 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -484,8 +484,17 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); if (rrb->cpp == 4) atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; - else + else switch (rrb->base._ActualFormat) { + case GL_RGB5: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; + break; + case GL_RGBA4: + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; + break; + case GL_RGB5_A1: + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; + break; + } cbpitch = (rrb->pitch / rrb->cpp); if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) @@ -585,6 +594,8 @@ static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) radeon_mipmap_level *lvl; int hastexture = 1; + if (!r200->state.texture.unit[i].unitneeded) + hastexture = 0; if (!t) hastexture = 0; else { @@ -620,6 +631,30 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); + uint32_t dwords = 3; + int i = atom->idx, j; + radeonTexObj *t = r200->state.texture.unit[i].texobj; + radeon_mipmap_level *lvl; + + BEGIN_BATCH_NO_AUTOSTATE(dwords + (3 * 5)); + /* XXX that size won't really match with image_override... */ + OUT_BATCH_TABLE(atom->cmd, 2); + + if (t && !t->image_override) { + lvl = &t->mt->levels[0]; + OUT_BATCH_TABLE((atom->cmd + 2), 1); + for (j = 1; j <= 5; j++) { + OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } + } + END_BATCH(); +} + +static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); uint32_t dwords = 2; int i = atom->idx, j; radeonTexObj *t = r200->state.texture.unit[i].texobj; @@ -752,7 +787,10 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); for (i = 0; i < 5; i++) - rmesa->hw.cube[i].emit = cube_emit; + if (rmesa->radeon.radeonScreen->kernel_mm) + rmesa->hw.cube[i].emit = cube_emit_cs; + else + rmesa->hw.cube[i].emit = cube_emit; } else { ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index ed1995e147..4e53672aee 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -834,7 +834,7 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo rImage->mt = NULL; } _mesa_init_teximage_fields(radeon->glCtx, target, texImage, - rb->width, rb->height, 1, 0, rb->cpp); + rb->base.Width, rb->base.Height, 1, 0, rb->cpp); texImage->RowStride = rb->pitch / rb->cpp; texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, internalFormat, @@ -866,8 +866,8 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo t->pp_txfilter |= tx_table_le[MESA_FORMAT_RGB565].filter; break; } - t->pp_txsize = ((rb->width - 1) << RADEON_TEX_USIZE_SHIFT) - | ((rb->height - 1) << RADEON_TEX_VSIZE_SHIFT); + t->pp_txsize = ((rb->base.Width - 1) << RADEON_TEX_USIZE_SHIFT) + | ((rb->base.Height - 1) << RADEON_TEX_VSIZE_SHIFT); t->pp_txformat |= R200_TXFORMAT_NON_POWER2; t->pp_txpitch = pitch_val; t->pp_txpitch -= 32; |