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path: root/src/gallium/drivers/cell/ppu/cell_gen_fp.c
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2009-12-08cell: use boolean instead of boolRoland Scheidegger
2009-12-02cell: fix TGSI breakageBrian Paul
2009-11-24tgsi: rename fields of tgsi_full_src_register to reduce verbosityKeith Whitwell
SrcRegister -> Register SrcRegisterInd -> Indirect SrcRegisterDim -> Dimension SrcRegisterDimInd -> DimIndirect
2009-11-24tgsi: rename fields of tgsi_full_dst_register to reduce verbosityKeith Whitwell
DstRegister -> Register DstRegisterInd -> Indirect
2009-11-24tgsi: rename fields of tgsi_full_declaration to reduce verbosityKeith Whitwell
DeclarationRange -> Range
2009-11-24tgsi: rename fields of tgsi_full_instruction to avoid excessive verbosityKeith Whitwell
InstructionPredicate -> Predicate InstructionLabel -> Label InstructionTexture -> Texture FullSrcRegisters -> Src FullDstRegisters -> Dst
2009-10-23gallium: remove the swizzling parts of ExtSwizzleKeith Whitwell
These haven't been used by the mesa state tracker since the conversion to tgsi_ureg, and it seems that none of the other state trackers are using it either. This helps simplify one of the biggest suprises when starting off with TGSI shaders.
2009-10-20cell: fix compilation on cellMarc Dietrich
s/LERP/LRP/
2009-08-30cell: fix compilationMarc Dietrich
2009-07-31Rename TGSI LOOP instruction to better match theri usage.Michal Krol
The LOOP/ENDLOOP pair is renamed to BGNFOR/ENDFOR as its behaviour is similar to a C language for-loop. The BGNLOOP2/ENDLOOP2 pair is renamed to BGNLOOP/ENDLOOP as now there is no name collision.
2009-07-22gallium: simplify tgsi_full_immediate structKeith Whitwell
Remove the need to have a pointer in this struct by just including the immediate data inline. Having a pointer in the struct introduces complications like needing to alloc/free the data pointed to, uncertainty about who owns the data, etc. There doesn't seem to be a need for it, and it is unlikely to make much difference plus or minus to performance. Added some asserts as we now will trip up on immediates with more than four elements. There were actually already quite a few such asserts, but the >4 case could be used in the future to specify indexable immediate ranges, such as lookup tables.
2009-01-10cell: use tgsi_dump_instruction() instead of spe_comment()Brian Paul
2009-01-05cell: fix code emit for RSQ/RCP when src arg == dst argBrian Paul
Fixes moire-like artifacts seen in fslight demo.
2009-01-04cell: initial codegen support for fragment shader loopsBrian Paul
Basic for/while loops work now. Only one level of loop nesting is supported at this time (same for if/else). The progs/glsl/mandelbrot demo works, but the colors are too dim.
2009-01-04cell: clean-up, improve SPU code generationBrian Paul
Start on ARL and address-relative indexing too.
2008-11-11cell: implement NRM3 opcodeBrian Paul
2008-10-29cell: add scalar param to emit_function_call() to indicate scalar function callsBrian Paul
Scalar calls only use the X component of the src regs and smear the result across the dest register's X/Y/Z/W.
2008-10-22cell: note that dst reg writing needs clampingBrian Paul
2008-10-16cell: implement KIL instructionBrian Paul
2008-10-16cell: clean up various texture-related thingsBrian Paul
Distinguish among texture targets in codegen. progs/demos/cubemap.c runs correctly now too.
2008-10-14cell: fall-through case for TGSI_OPCODE_TXBBrian Paul
2008-10-10cell: more instruction scheduling optimizations (MIN/MAX/LERP/etc)Brian Paul
Also, optimize register->memory stores.
2008-10-10cell: pass texture unit (sampler number) to txp() functionBrian Paul
The glsl/multitex demo runs now.
2008-10-10cell: fix function prologue/epilogue code for large stack framesBrian Paul
The ai instruction is limited to a 10-bit signed immediate value.
2008-10-10cell: fix LERP when dst reg is a src regBrian Paul
Also, bump up frame size and fix some assertions.
2008-10-10cell: fix fm/fs copy & paste bug from a few commits agoBrian Paul
2008-10-10cell: fix bug in emit_FLR() when src reg == dst regBrian Paul
2008-10-10cell: fix bug in emit_FRC() when src register == dst register.Brian Paul
With this fix, the glsl/brick demo runs.
2008-10-09cell: implement basic TXP instruction in fragment shadersBrian Paul
Lots of restrictions for now (one 2D texture, no mipmaps, etc.) for now but basic texture demos work. TEX, TXD, TXP do the same thing for the time being.
2008-10-09cell: better immediate value allocation, better commentsBrian Paul
2008-10-09cell: massage the emit functions to get better instruction schedulingBrian Paul
2008-10-08cell: implement function calls from shader code. fslight demo runs now.Brian Paul
Used for SIN, COS, EXP2, LOG2, POW instructions. TEX next. Fixed some bugs in MIN, MAX, DP3, DP4, DPH instructions. In rtasm code: Special-case spe_lqd(), spe_stqd() functions so they take byte offsets but low-order 4 bits are shifted out. This makes things consistant with SPU assembly language conventions. Added spe_get_registers_used() function.
2008-10-07cell: add support for fragment shader constant buffersBrian Paul
2008-10-07cell: fix incorrect extended swizzle term code in get_src_reg()Brian Paul
2008-10-07cell: fix formattingBrian Paul
2008-09-26cell: checkpoint: more work in emit_function_call()Brian Paul
Simple function call works now, but we don't save/restore the caller's registers yet.
2008-09-26cell: checkpoint: support for function calls in SPU shadersBrian Paul
Will be used for instructions like SIN/COS/POW/TEX/etc. The PPU needs to know the address of some functions in the SPU address space. Send that info to the PPU/main memory rather than patch up shaders on the SPU side. Not finished/tested yet...
2008-09-22cell: Fixed bug with absolute, negate, set-negative logic in source fetch ↵Jonathan White
for TGSI instructions. The logic should operate on the origin channel not the swizzled channel. Please enter the commit message for your changes.
2008-09-22cell: Added TRUNC, SWZ (extended) and XPD instructions, verified against ↵Jonathan White
softpipe. Optimized FLR and FRC. Fixed writeback logic for DP3, DP4 and DPH.
2008-09-22cell: Added DPH instruction and verified against softpipe.Jonathan White
2008-09-19cell: Added FRC instructionJonathan White
2008-09-19cell: Added FLR instruction. Verified the following instructions match ↵Jonathan White
softpipe: MOV, ADD, MUL, SGE, SUB, MAD, ABS, SLT, MIN, MAX, LRP, DP3, DP4, CMP, FLR
2008-09-19cell: Fixed bugs with DP3 and DP4, they match softpipe results now.Jonathan White
2008-09-19cell: change spe_complement() to take a src and dst reg, like other instructionsBrian Paul
2008-09-18cell: Added CMP instructionJonathan White
2008-09-18cell: Fix bug with complement logic for SGE and SLEJonathan White
2008-09-18cell: Added SGE and SLE instructions to dispatch functionJonathan White
2008-09-18cell: Added SGE and SLE instructionsJonathan White
2008-09-16cell: Added RCP and RSQ instruction support.Jonathan White
2008-09-16cell: Added DP3 and DP4 instructionsJonathan White
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