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Thomas White
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i965
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brw_structs.h
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2009-09-02
i965: CS FENCE in URB_FENCE is 11-bits wide
Xiang, Haihao
2009-08-04
i965: Spell "conditional" correctly.
Eric Anholt
2009-08-04
i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.
Eric Anholt
2009-07-13
i965: add support for new chipsets
Xiang, Haihao
2009-06-30
i965: move BRW_MAX_GRF, define BRW_MAX_MRF
Brian Paul
2009-06-17
i965: Fall back or appropriately adjust offsets of drawing to tiled regions.
Eric Anholt
2009-02-25
i965: Rename CMD_CONST_BUFFER_STATE to the CS_URB_STATE used in the docs.
Eric Anholt
2009-01-28
i965: minor comments
Brian Paul
2008-11-02
i965: Merge GM45 into the G4X chipset define.
Eric Anholt
2008-07-08
i965: official name for GM45 chipset
Xiang, Haihao
2008-01-29
i965: new integrated graphics chipset support
Xiang, Haihao
2007-12-17
[965] Simplify scissor handling by using DrawBuffer values.
Eric Anholt
2007-12-14
[965] Replace the state cache suballocator with direct dri_bufmgr use.
Eric Anholt
2007-01-06
i965: Avoid branch instructions while in single program flow mode.
Eric Anholt
2006-08-09
Add Intel i965G/Q DRI driver.
Eric Anholt
