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As part of the DRI driver interface rewrite I merged __DRIscreenPrivate
and __DRIscreen, and likewise for __DRIdrawablePrivate and
__DRIcontextPrivate. I left typedefs in place though, to avoid renaming
all the *Private use internal to the driver. That was probably a
mistake, and it turns out a one-line find+sed combo can do the mass
rename. Better late than never.
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Tested on r300 only, other cards may require adjusting texture_compressed_row_align.
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_ActualFormat is replaced by Format (MESA_FORMAT_x).
ColorEncoding, ComponentType, RedBits, GreenBits, BlueBits, etc. are
all replaced by MESA_FORMAT_x queries.
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- max texture size is 8k, but mesa doesn't support
that at the moment.
- attempt to set shader limits to what the hw actually
supports
- clean up some old r300 cruft
- no need to explicitly disable irqs. This is fixed
in the drm now.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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This reverts commit 651cffd626a82d9bf539437ca4bdf8ea4b396fab.
The commit inadvertantly introduced a new gallium dependency on the meta code.
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I inherited this and really it stayed around far too long,
make it nice and simple.
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Converted r100 to use shared debug code with sed and fast compile check. New
code has compability layer so old debugging code doesn't have to be changed
all immidiatly.
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switches more state handling to common code. We need
should be more fine grained with the state atoms
eventually.
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We keep dma buffer objects in list untill they have been unused for many
draw operations. Current limit of having 100 flushes is just guess for
good performance/memory trade off.
Moving WARN_ONCE macro to common context because it is used in multiple drivers.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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Move to common code base so radeon/r200 can add support for this.
Make OQ start a state emitted like all normal state, and make no-tcl
flushing work in proper places.
Really need a generic post emit space reservation mechanism like max_state
so we can reserve some space for the emit
this code passes demos/arbocclude, piglit occlusion query and
glean occlusion query with TCL and NO-TCL on my rv530.
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This stuff was a vestige of the r600 bring up and
now mostly serves to periodically break the build.
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Reference counting protects DRM lock call from recursive locking that would
cause hang. Code also adds optional debugging output for recursive call that
is compiled only if NDEBUG is not defined.
This code is not 100% thread safe because mesa doesn't include increment and
test atomic operation. There is built-in gcc functions but they are only
available from gcc 4.2.
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Only really got good testing on r500 so far, need to enable in
DDX and play some more.
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This almost fixes compressed mipmapped textures on r200, though some small
mip levels are still broken.
Leave r300 compressed texture stride as is though afaik it's different
to pre-radeon-rewrite too. Also do the fixup for rs600 uncompressed row stride
at same place.
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fixes texwrap
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This fixes problem that glxinfo was reporting r600+ cards as unknown.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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patch from Kevin DeKorte with some minor fixes from me.
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into r6xx-rewrite
This builds, but I get an assertion in radeonGetLock() due to
the drawable being null.
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Move all the metaops to a dri_metaops file and port radeon/intel
to use the new common meta ops code.
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Port fixes to read buffer from front.
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half stealing the code without taking the intel regions
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This fixes an assertion in glReadPixels from the front buffer.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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Display the chip family and PCI ID. This can be parsed easily,
and essentially all information that the driver has about the chip can be
deduced from it.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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The duplication of state data caused a crash due to double-free on destruction
of context, because a variable wasn't correctly null'ed out.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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Fixes
glxinfo: main/renderbuffer.c:2159: _mesa_reference_renderbuffer: Assertion
`oldRb->Magic == 0xaabbccdd' failed.
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Basically the same as 43d9020ff1e975e7f4f9480d9ef24f0b9fb2141f for intel. Bug 21688.
Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
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Looks like r400 based IGP chips require 64 byte alignment
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This fixes up the buffer validation scheme, so that we keep a list
of buffers to validate so cmdbuf flushes during a pipeline get
all the buffers revalidated on the next emit.
This also fixes radeonFlush to not flush unless we have something
useful to send to the GPU, like a DMA buffer or something not state
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Context destruction was nearly the same over all the drivers,
so collapse it down.
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this fixes qtdemo-qt4 starting and a leak in glxgears exit
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This is because the DDX always allocates using the drawable sizes.
which gives me twice the depth buffer I asked for, dumb.
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Re work depth issues.
Do a lot more FBO abstactions
fixup depth/stencil buffer interactions
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