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authorYoshinori Sato <ysato@users.sourceforge.jp>2006-11-05 15:40:13 +0900
committerPaul Mundt <lethal@linux-sh.org>2006-12-06 10:45:36 +0900
commit9d4436a6fbc8c5eccdfcb8f5884e0a7b4a57f6d2 (patch)
treea8b7532fffa76ae526dea547cc87200466e00842 /arch/sh/kernel/timers
parente62438630ca37539c8cc1553710bbfaa3cf960a7 (diff)
sh: Add support for SH7206 and SH7619 CPU subtypes.
This implements initial support for the SH7206 (SH-2A) and SH7619 (SH-2) MMU-less CPUs. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/timers')
-rw-r--r--arch/sh/kernel/timers/Makefile2
-rw-r--r--arch/sh/kernel/timers/timer-cmt.c256
-rw-r--r--arch/sh/kernel/timers/timer-mtu2.c260
-rw-r--r--arch/sh/kernel/timers/timer.c6
4 files changed, 524 insertions, 0 deletions
diff --git a/arch/sh/kernel/timers/Makefile b/arch/sh/kernel/timers/Makefile
index 151a6a304ce..bcf244ff6a1 100644
--- a/arch/sh/kernel/timers/Makefile
+++ b/arch/sh/kernel/timers/Makefile
@@ -5,4 +5,6 @@
obj-y := timer.o
obj-$(CONFIG_SH_TMU) += timer-tmu.o
+obj-$(CONFIG_SH_MTU2) += timer-mtu2.o
+obj-$(CONFIG_SH_CMT) += timer-cmt.o
diff --git a/arch/sh/kernel/timers/timer-cmt.c b/arch/sh/kernel/timers/timer-cmt.c
new file mode 100644
index 00000000000..9eab395cd34
--- /dev/null
+++ b/arch/sh/kernel/timers/timer-cmt.c
@@ -0,0 +1,256 @@
+/*
+ * arch/sh/kernel/timers/timer-cmt.c - CMT Timer Support
+ *
+ * Copyright (C) 2005 Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/seqlock.h>
+#include <asm/timer.h>
+#include <asm/rtc.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/clock.h>
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define CMT_CMSTR 0xf84a0070
+#define CMT_CMCSR_0 0xf84a0072
+#define CMT_CMCNT_0 0xf84a0074
+#define CMT_CMCOR_0 0xf84a0076
+#define CMT_CMCSR_1 0xf84a0078
+#define CMT_CMCNT_1 0xf84a007a
+#define CMT_CMCOR_1 0xf84a007c
+
+#define STBCR3 0xf80a0000
+#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0)
+#define CMT_CMCSR_INIT 0x0040
+#define CMT_CMCSR_CALIB 0x0000
+#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
+#define CMT_CMSTR 0xfffec000
+#define CMT_CMCSR_0 0xfffec002
+#define CMT_CMCNT_0 0xfffec004
+#define CMT_CMCOR_0 0xfffec006
+
+#define STBCR4 0xfffe040c
+#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR4) & ~0x04, STBCR4); } while(0)
+#define CMT_CMCSR_INIT 0x0040
+#define CMT_CMCSR_CALIB 0x0000
+#else
+#error "Unknown CPU SUBTYPE"
+#endif
+
+static DEFINE_SPINLOCK(cmt0_lock);
+
+static unsigned long cmt_timer_get_offset(void)
+{
+ int count;
+ unsigned long flags;
+
+ static unsigned short count_p = 0xffff; /* for the first call after boot */
+ static unsigned long jiffies_p = 0;
+
+ /*
+ * cache volatile jiffies temporarily; we have IRQs turned off.
+ */
+ unsigned long jiffies_t;
+
+ spin_lock_irqsave(&cmt0_lock, flags);
+ /* timer count may underflow right here */
+ count = ctrl_inw(CMT_CMCOR_0);
+ count -= ctrl_inw(CMT_CMCNT_0);
+
+ jiffies_t = jiffies;
+
+ /*
+ * avoiding timer inconsistencies (they are rare, but they happen)...
+ * there is one kind of problem that must be avoided here:
+ * 1. the timer counter underflows
+ */
+
+ if (jiffies_t == jiffies_p) {
+ if (count > count_p) {
+ /* the nutcase */
+ if (ctrl_inw(CMT_CMCSR_0) & 0x80) { /* Check CMF bit */
+ count -= LATCH;
+ } else {
+ printk("%s (): hardware timer problem?\n",
+ __FUNCTION__);
+ }
+ }
+ } else
+ jiffies_p = jiffies_t;
+
+ count_p = count;
+ spin_unlock_irqrestore(&cmt0_lock, flags);
+
+ count = ((LATCH-1) - count) * TICK_SIZE;
+ count = (count + LATCH/2) / LATCH;
+
+ return count;
+}
+
+static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id,
+ struct pt_regs *regs)
+{
+ unsigned long timer_status;
+
+ /* Clear CMF bit */
+ timer_status = ctrl_inw(CMT_CMCSR_0);
+ timer_status &= ~0x80;
+ ctrl_outw(timer_status, CMT_CMCSR_0);
+
+ /*
+ * Here we are in the timer irq handler. We just have irqs locally
+ * disabled but we don't know if the timer_bh is running on the other
+ * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
+ * the irq version of write_lock because as just said we have irq
+ * locally disabled. -arca
+ */
+ write_seqlock(&xtime_lock);
+ handle_timer_tick(regs);
+ write_sequnlock(&xtime_lock);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction cmt_irq = {
+ .name = "timer",
+ .handler = cmt_timer_interrupt,
+ .flags = SA_INTERRUPT,
+ .mask = CPU_MASK_NONE,
+};
+
+/*
+ * Hah! We'll see if this works (switching from usecs to nsecs).
+ */
+static unsigned long cmt_timer_get_frequency(void)
+{
+ u32 freq;
+ struct timespec ts1, ts2;
+ unsigned long diff_nsec;
+ unsigned long factor;
+
+ /* Setup the timer: We don't want to generate interrupts, just
+ * have it count down at its natural rate.
+ */
+
+ ctrl_outw(ctrl_inw(CMT_CMSTR) & ~0x01, CMT_CMSTR);
+ ctrl_outw(CMT_CMCSR_CALIB, CMT_CMCSR_0);
+ ctrl_outw(0xffff, CMT_CMCOR_0);
+ ctrl_outw(0xffff, CMT_CMCNT_0);
+
+ rtc_sh_get_time(&ts2);
+
+ do {
+ rtc_sh_get_time(&ts1);
+ } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
+
+ /* actually start the timer */
+ ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR);
+
+ do {
+ rtc_sh_get_time(&ts2);
+ } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
+
+ freq = 0xffff - ctrl_inw(CMT_CMCNT_0);
+ if (ts2.tv_nsec < ts1.tv_nsec) {
+ ts2.tv_nsec += 1000000000;
+ ts2.tv_sec--;
+ }
+
+ diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
+
+ /* this should work well if the RTC has a precision of n Hz, where
+ * n is an integer. I don't think we have to worry about the other
+ * cases. */
+ factor = (1000000000 + diff_nsec/2) / diff_nsec;
+
+ if (factor * diff_nsec > 1100000000 ||
+ factor * diff_nsec < 900000000)
+ panic("weird RTC (diff_nsec %ld)", diff_nsec);
+
+ return freq * factor;
+}
+
+static void cmt_clk_init(struct clk *clk)
+{
+ u8 divisor = CMT_CMCSR_INIT & 0x3;
+ ctrl_inw(CMT_CMCSR_0);
+ ctrl_outw(CMT_CMCSR_INIT, CMT_CMCSR_0);
+ clk->parent = clk_get("module_clk");
+ clk->rate = clk->parent->rate / (8 << (divisor << 1));
+}
+
+static void cmt_clk_recalc(struct clk *clk)
+{
+ u8 divisor = ctrl_inw(CMT_CMCSR_0) & 0x3;
+ clk->rate = clk->parent->rate / (8 << (divisor << 1));
+}
+
+static struct clk_ops cmt_clk_ops = {
+ .init = cmt_clk_init,
+ .recalc = cmt_clk_recalc,
+};
+
+static struct clk cmt0_clk = {
+ .name = "cmt0_clk",
+ .ops = &cmt_clk_ops,
+};
+
+static int cmt_timer_start(void)
+{
+ ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR);
+ return 0;
+}
+
+static int cmt_timer_stop(void)
+{
+ ctrl_outw(ctrl_inw(CMT_CMSTR) & ~0x01, CMT_CMSTR);
+ return 0;
+}
+
+static int cmt_timer_init(void)
+{
+ unsigned long interval;
+
+ cmt_clock_enable();
+
+ setup_irq(TIMER_IRQ, &cmt_irq);
+
+ cmt0_clk.parent = clk_get("module_clk");
+
+ cmt_timer_stop();
+
+ interval = cmt0_clk.parent->rate / 8 / HZ;
+ printk(KERN_INFO "Interval = %ld\n", interval);
+
+ ctrl_outw(interval, CMT_CMCOR_0);
+
+ clk_register(&cmt0_clk);
+ clk_enable(&cmt0_clk);
+
+ cmt_timer_start();
+
+ return 0;
+}
+
+struct sys_timer_ops cmt_timer_ops = {
+ .init = cmt_timer_init,
+ .start = cmt_timer_start,
+ .stop = cmt_timer_stop,
+ .get_frequency = cmt_timer_get_frequency,
+ .get_offset = cmt_timer_get_offset,
+};
+
+struct sys_timer cmt_timer = {
+ .name = "cmt",
+ .ops = &cmt_timer_ops,
+};
+
diff --git a/arch/sh/kernel/timers/timer-mtu2.c b/arch/sh/kernel/timers/timer-mtu2.c
new file mode 100644
index 00000000000..73a5ef3c457
--- /dev/null
+++ b/arch/sh/kernel/timers/timer-mtu2.c
@@ -0,0 +1,260 @@
+/*
+ * arch/sh/kernel/timers/timer-mtu2.c - MTU2 Timer Support
+ *
+ * Copyright (C) 2005 Paul Mundt
+ *
+ * Based off of arch/sh/kernel/timers/timer-tmu.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/seqlock.h>
+#include <asm/timer.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/clock.h>
+
+/*
+ * We use channel 1 for our lowly system timer. Channel 2 would be the other
+ * likely candidate, but we leave it alone as it has higher divisors that
+ * would be of more use to other more interesting applications.
+ *
+ * TODO: Presently we only implement a 16-bit single-channel system timer.
+ * However, we can implement channel cascade if we go the overflow route and
+ * get away with using 2 MTU2 channels as a 32-bit timer.
+ */
+
+static DEFINE_SPINLOCK(mtu2_lock);
+
+#define MTU2_TSTR 0xfffe4280
+#define MTU2_TCR_1 0xfffe4380
+#define MTU2_TMDR_1 0xfffe4381
+#define MTU2_TIOR_1 0xfffe4382
+#define MTU2_TIER_1 0xfffe4384
+#define MTU2_TSR_1 0xfffe4385
+#define MTU2_TCNT_1 0xfffe4386 /* 16-bit counter */
+#define MTU2_TGRA_1 0xfffe438a
+
+#define STBCR3 0xfffe0408
+
+#define MTU2_TSTR_CST1 (1 << 1) /* Counter Start 1 */
+
+#define MTU2_TSR_TGFA (1 << 0) /* GRA compare match */
+
+#define MTU2_TIER_TGIEA (1 << 0) /* GRA compare match interrupt enable */
+
+#define MTU2_TCR_INIT 0x22
+
+#define MTU2_TCR_CALIB 0x00
+
+static unsigned long mtu2_timer_get_offset(void)
+{
+ int count;
+ unsigned long flags;
+
+ static int count_p = 0x7fff; /* for the first call after boot */
+ static unsigned long jiffies_p = 0;
+
+ /*
+ * cache volatile jiffies temporarily; we have IRQs turned off.
+ */
+ unsigned long jiffies_t;
+
+ spin_lock_irqsave(&mtu2_lock, flags);
+ /* timer count may underflow right here */
+ count = ctrl_inw(MTU2_TCNT_1); /* read the latched count */
+
+ jiffies_t = jiffies;
+
+ /*
+ * avoiding timer inconsistencies (they are rare, but they happen)...
+ * there is one kind of problem that must be avoided here:
+ * 1. the timer counter underflows
+ */
+
+ if (jiffies_t == jiffies_p) {
+ if (count > count_p) {
+ if (ctrl_inb(MTU2_TSR_1) & MTU2_TSR_TGFA) {
+ count -= LATCH;
+ } else {
+ printk("%s (): hardware timer problem?\n",
+ __FUNCTION__);
+ }
+ }
+ } else
+ jiffies_p = jiffies_t;
+
+ count_p = count;
+ spin_unlock_irqrestore(&mtu2_lock, flags);
+
+ count = ((LATCH-1) - count) * TICK_SIZE;
+ count = (count + LATCH/2) / LATCH;
+
+ return count;
+}
+
+static irqreturn_t mtu2_timer_interrupt(int irq, void *dev_id,
+ struct pt_regs *regs)
+{
+ unsigned long timer_status;
+
+ /* Clear TGFA bit */
+ timer_status = ctrl_inb(MTU2_TSR_1);
+ timer_status &= ~MTU2_TSR_TGFA;
+ ctrl_outb(timer_status, MTU2_TSR_1);
+
+ /* Do timer tick */
+ write_seqlock(&xtime_lock);
+ handle_timer_tick(regs);
+ write_sequnlock(&xtime_lock);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction mtu2_irq = {
+ .name = "timer",
+ .handler = mtu2_timer_interrupt,
+ .flags = SA_INTERRUPT,
+ .mask = CPU_MASK_NONE,
+};
+
+/*
+ * Hah! We'll see if this works (switching from usecs to nsecs).
+ */
+static unsigned long mtu2_timer_get_frequency(void)
+{
+ u32 freq;
+ struct timespec ts1, ts2;
+ unsigned long diff_nsec;
+ unsigned long factor;
+
+ /* Setup the timer: We don't want to generate interrupts, just
+ * have it count down at its natural rate.
+ */
+
+ ctrl_outb(ctrl_inb(MTU2_TSTR) & ~MTU2_TSTR_CST1, MTU2_TSTR);
+ ctrl_outb(MTU2_TCR_CALIB, MTU2_TCR_1);
+ ctrl_outb(ctrl_inb(MTU2_TIER_1) & ~MTU2_TIER_TGIEA, MTU2_TIER_1);
+ ctrl_outw(0, MTU2_TCNT_1);
+
+ rtc_get_time(&ts2);
+
+ do {
+ rtc_get_time(&ts1);
+ } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
+
+ /* actually start the timer */
+ ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR);
+
+ do {
+ rtc_get_time(&ts2);
+ } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
+
+ freq = ctrl_inw(MTU2_TCNT_0);
+ if (ts2.tv_nsec < ts1.tv_nsec) {
+ ts2.tv_nsec += 1000000000;
+ ts2.tv_sec--;
+ }
+
+ diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
+
+ /* this should work well if the RTC has a precision of n Hz, where
+ * n is an integer. I don't think we have to worry about the other
+ * cases. */
+ factor = (1000000000 + diff_nsec/2) / diff_nsec;
+
+ if (factor * diff_nsec > 1100000000 ||
+ factor * diff_nsec < 900000000)
+ panic("weird RTC (diff_nsec %ld)", diff_nsec);
+
+ return freq * factor;
+}
+
+static unsigned int divisors[] = { 1, 4, 16, 64, 1, 1, 256 };
+
+static void mtu2_clk_init(struct clk *clk)
+{
+ u8 idx = MTU2_TCR_INIT & 0x7;
+
+ clk->rate = clk->parent->rate / divisors[idx];
+ /* Start TCNT counting */
+ ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
+
+}
+
+static void mtu2_clk_recalc(struct clk *clk)
+{
+ u8 idx = ctrl_inb(MTU2_TCR_1) & 0x7;
+ clk->rate = clk->parent->rate / divisors[idx];
+}
+
+static struct clk_ops mtu2_clk_ops = {
+ .init = mtu2_clk_init,
+ .recalc = mtu2_clk_recalc,
+};
+
+static struct clk mtu2_clk1 = {
+ .name = "mtu2_clk1",
+ .ops = &mtu2_clk_ops,
+};
+
+static int mtu2_timer_start(void)
+{
+ ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
+ return 0;
+}
+
+static int mtu2_timer_stop(void)
+{
+ ctrl_outb(ctrl_inb(MTU2_TSTR) & ~MTU2_TSTR_CST1, MTU2_TSTR);
+ return 0;
+}
+
+static int mtu2_timer_init(void)
+{
+ u8 tmp;
+ unsigned long interval;
+
+ setup_irq(TIMER_IRQ, &mtu2_irq);
+
+ mtu2_clk1.parent = clk_get("module_clk");
+
+ ctrl_outb(ctrl_inb(STBCR3) & (~0x20), STBCR3);
+
+ /* Normal operation */
+ ctrl_outb(0, MTU2_TMDR_1);
+ ctrl_outb(MTU2_TCR_INIT, MTU2_TCR_1);
+ ctrl_outb(0x01, MTU2_TIOR_1);
+
+ /* Enable underflow interrupt */
+ ctrl_outb(ctrl_inb(MTU2_TIER_1) | MTU2_TIER_TGIEA, MTU2_TIER_1);
+
+ interval = CONFIG_SH_PCLK_FREQ / 16 / HZ;
+ printk(KERN_INFO "Interval = %ld\n", interval);
+
+ ctrl_outw(interval, MTU2_TGRA_1);
+ ctrl_outw(0, MTU2_TCNT_1);
+
+ clk_register(&mtu2_clk1);
+ clk_enable(&mtu2_clk1);
+
+ return 0;
+}
+
+struct sys_timer_ops mtu2_timer_ops = {
+ .init = mtu2_timer_init,
+ .start = mtu2_timer_start,
+ .stop = mtu2_timer_stop,
+ .get_frequency = mtu2_timer_get_frequency,
+ .get_offset = mtu2_timer_get_offset,
+};
+
+struct sys_timer mtu2_timer = {
+ .name = "mtu2",
+ .ops = &mtu2_timer_ops,
+};
diff --git a/arch/sh/kernel/timers/timer.c b/arch/sh/kernel/timers/timer.c
index dc1f631053a..a6bcc913d25 100644
--- a/arch/sh/kernel/timers/timer.c
+++ b/arch/sh/kernel/timers/timer.c
@@ -17,6 +17,12 @@ static struct sys_timer *sys_timers[] __initdata = {
#ifdef CONFIG_SH_TMU
&tmu_timer,
#endif
+#ifdef CONFIG_SH_MTU2
+ &mtu2_timer,
+#endif
+#ifdef CONFIG_SH_CMT
+ &cmt_timer,
+#endif
NULL,
};