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authorDave Airlie <airlied@redhat.com>2009-09-18 14:31:48 +1000
committerDave Airlie <airlied@redhat.com>2009-09-18 14:34:06 +1000
commit65cb15a686cedab52abc336d7a400fe3a110ac4c (patch)
tree307f12f572747f0d93f385e4dc049a407feb29e0 /drivers/gpu
parentb15591f3120309093fc6d3df26b4242187d7b384 (diff)
drm/radeon: avivo chips have no separate int bit for display
display interrupts are not enabled via this register, the DISPLAY_INT bit is a status only to show that other regs need to be read. Noticed by Alex Deucher Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/rs600.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index c31bd843925..6af0331cae0 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -272,11 +272,9 @@ int rs600_irq_set(struct radeon_device *rdev)
tmp |= RADEON_SW_INT_ENABLE;
}
if (rdev->irq.crtc_vblank_int[0]) {
- tmp |= AVIVO_DISPLAY_INT_STATUS;
mode_int |= AVIVO_D1MODE_INT_MASK;
}
if (rdev->irq.crtc_vblank_int[1]) {
- tmp |= AVIVO_DISPLAY_INT_STATUS;
mode_int |= AVIVO_D2MODE_INT_MASK;
}
WREG32(RADEON_GEN_INT_CNTL, tmp);