diff options
| author | Maciej Cencora <m.cencora@gmail.com> | 2009-05-02 17:27:03 +0200 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2009-05-04 12:09:36 -0400 |
| commit | 0b22615c2c860968a027c04519e25864ae69f6cd (patch) | |
| tree | 88ea6ba2f202f49dcf70335dc6097027da3b38c2 /src/mesa/drivers/dri/r300/r300_context.c | |
| parent | 55db6ce537f1fd9acf205400202abfcc3908d6c3 (diff) | |
r300: set proper texture row alignment for IGP chips
Looks like r400 based IGP chips require 64 byte alignment
Diffstat (limited to 'src/mesa/drivers/dri/r300/r300_context.c')
| -rw-r--r-- | src/mesa/drivers/dri/r300/r300_context.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 4d1f10ba4d..70c7730be9 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -412,6 +412,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, if (r300->radeon.radeonScreen->kernel_mm) driInitExtensions(ctx, mm_extensions, GL_FALSE); + if (screen->chip_family == CHIP_FAMILY_RS600 || screen->chip_family == CHIP_FAMILY_RS690 || + screen->chip_family == CHIP_FAMILY_RS740) { + r300->radeon.texture_row_align = 64; + } + r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy"); |